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MK712RITR Datasheet(PDF) 2 Page - Integrated Circuit Systems

Part # MK712RITR
Description  Touch Screen Controller
PDF  16 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

MK712RITR Datasheet(HTML) 2 Page - Integrated Circuit Systems

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MK712
Touch Screen Controller
MDS 712 I
2
Revision 100899
Printed 11/16/00
Integrated Circuit Systems, Inc.•525 Race St.•San Jose•CA•95126•(408)295-9800tel•www.icst.com
I C R O
C LOC K
Number
Name
Type
Description
1
NC
-
No Connect
2
INT
O
Interrupt. Goes high to signal an interrupt. Cleared on next read.
3
TOUCH
O
Touch signal. Goes low when screen is touched. Goes high when not touched.
4
VDD
P
Connect to +5V or +3.3V.*
5
VDD
P
Connect to +5V or +3.3V.*
6
XH
TS
Connect to X-high on touch screen. (Right side)
7
XL
TS
Connect to X-low on touch screen. (Left side)
8
YH
TS
Connect to Y-high on touch screen. (Top)
9
YL
TS
Connect to Y-low on touch screen. (Bottom)
10
GND
P
Connect to ground.
11
GND
P
Connect to ground.
12
WR
I
Write enable. Active low.
13
RD
I
Read enable. Active low.
14
CS
I
Chip select. Active low.
15
A2
I
Register address 2.
16
A1
I
Register address 1.
17
A0
I
Register address 0.
18
CLKIN
I
Clock input. Typically 14.3 MHz. Best if driven by a MicroClock clock synthesizer.
19
D7
I/O
Data bit 7.
20
D6
I/O
Data bit 6.
21
GND
P
Connect to ground.
22
VDD
P
Connect to +5V or +3.3V.*
23
D5
I/O
Data bit 5.
24
D4
I/O
Data bit 4.
25
D3
I/O
Data bit 3.
26
D2
I/O
Data bit 2.
27
D1
I/O
Data bit 1.
28
D0
I/O
Data bit 0.
Pin Descriptions
Key: I = Input, O = Output, I/O = Input and Output, P = Power, TS = Touch Screen pin..
*Note: All VDD’s must be connected to the same voltage.
Interrupts
Interrupts are controlled by register 6 (see Register Description). The INT pin (pin 2) goes high to
signal an interrupt. Interrupts are then cleared by reading any register. However, if the MK712 is in the
process of generating an interrupt during a read cycle, then the interrupt is not cleared and INT will stay
high. This internal process may take 100ns, and so to guarantee that the interrupt is cleared, two
successive read cycles may be necessary.



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