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MK74CB44R Datasheet(PDF) 3 Page - Integrated Circuit Systems

Part # MK74CB44R
Description  Quad 1 to 4 Buffalo??Clock Driver
PDF  5 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

MK74CB44R Datasheet(HTML) 3 Page - Integrated Circuit Systems

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MK74CB44
Quad 1 to 4 Buffalo™ Clock Driver
MDS 74CB44 B
3
Revision 022000
Printed 11/17/00
Integrated Circuit Systems, Inc. • 525 Race St. • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
PRELIMINARY INFORMATION
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
0.5
VDD+0.5
V
Clock Outputs
Referenced to GND
0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 20 seconds
260
°C
Storage Temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
Operating Voltage, VDD
3.0
3.3
5.5
V
Input High Voltage, VIH
VDD-1
VDD/2
V
Input Low Voltage, VIL
VDD/2
1
V
Output High Voltage
IOH=-8mA
VDD-0.4
V
Output High Voltage
IOH=-12mA
2.4
V
Output Low Voltage
IOL=12mA
0.8
V
Operating Supply Current, IDD, at 100 MHz
No Load
55
mA
Output Impedance
14
Ω
Short Circuit Current
Each output
50
mA
Input Capacitance
7
pF
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
Input Clock Frequency
Note 4, 5
0
200
MHz
Propagation Delay with load=15pF
1.4
3
ns
Output Clock Rise Time
0.8 to 2.0V
2
ns
Output Clock Fall Time
2.0 to 0.8V
2
ns
Output Clock Rising Edge Skew
At VDD/2. Note 2
100
250
ps
Output Clock Bank to Bank Skew
At VDD/2. Note 3
100
250
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Within any bank of four outputs, with equal loading.
3. Between any two banks of four with their inputs connected together, and equal loading.
4. At VDD = 3.3 V, 70°C, series termination of 33
Ω per pin, 8 pF load per pin.
5. See discussion and graph of speed versus load.



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