MK74ZD133

PLL and 32-Output Clock Driver

PRELIMINARY

INFORMATION

MDS 74ZD133 C

5

Revision 010899

Printed 11/17/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com

Address

S4

S3

S2

S1

S0

Input (F)

Input (Y)

Output

0

0

0

0

0

0

20

20

90*

1

0

0

0

0

1

20

20

30

2

0

0

0

1

0

20

20

81*

3

0

0

0

1

1

20

20

25

4

0

0

1

0

0

20

20

54

5

0

0

1

0

1

20

20

50

6

0

0

1

1

0

20

20

33.33

7

0

0

1

1

1

20

20

27

8

0

1

0

0

0

20

20

64

9

0

1

0

0

1

20

20

75

10

0

1

0

1

0

20

20

83.33*

11

0

1

0

1

1

20

20

66.66

12

0

1

1

0

0

20

20

133.33*

13

0

1

1

0

1

20

20

62.5

14

0

1

1

1

0

20

20

31.25

15

0

1

1

1

1

20

20

125*

16

1

0

0

0

0

20

20

55

17

1

0

0

0

1

20

20

53.125

18

1

0

0

1

0

20

20

135*

19

1

0

0

1

1

20

20

106.25*

20

1

0

1

0

0

20

20

106*

21

1

0

1

0

1

20

20

106.25*

22

1

0

1

1

0

20

20

106.66*

23

1

0

1

1

1

20

20

107*

24

1

1

0

0

0

7 - 26.5

7 - 44.44

x3

25

1

1

0

0

1

3 - 10

3 - 16.67

x8

26

1

1

0

1

0

4 - 13.33

4 - 22.22

x6

27

1

1

0

1

1

5 - 16

5 - 26.67

x5

28

1

1

1

0

0

reserved

reserved

reserved

29

1

1

1

0

1

10 - 40

10 - 66.67

x2

30

1

1

1

1

0

6 - 20

6 - 33.33

x4

31

1

1

1

1

1

20 - 80

20 - 100

x1

Output Frequency Select Table

The MK74ZD133 has two primary

modes of operation: “Clock Generator”

and “Zero Delay Multiplier”.

In Clock Generator mode, addresses 0

through 23, specific output frequencies

are generated from a 20 MHz input.

There is no fixed phase relationship

between the input and output clocks.

In Zero Delay Multiplier mode,

addresses 24 through 31, the output

frequency is a simple integer multiple of

the input. The input range can vary over

several MHz, making it possible to

generate output frequencies that are not

included in Clock Generator mode. In

this mode, FBOUT3 is fed back to the

FBIN pin, and the rising edges of the

input and outputs are synchronized.

Configuring the Input/Output

Pins

The MK74ZD133 uses I/O pins whose

status as select inputs are sampled upon

power-up. The chip then selects this

address in the table to the left, and stays

in that configuration until a new power-

up sequence, when the select inputs are

sampled again. These pins all have

internal pull-up resistors, so the 10k

Ω

resistor is only needed to connect to

ground for the 0 selection in the table

(as shown below).

Output Frequency Generation

to load

I/O

For select

= 0 (low)

10k

Ω

33

Ω

Don’t stuff 10k

for“1” selection

* These modes only guaranteed in the Y (LQFP) package