IDT71256 datasheet(3/8 Pages) IDT

3 / 8 page

6.42

IDT71256SA

CMOS Static RAM 256K (32K x 8-Bit)

Commercial and Industrial Temperature Ranges

Figure 2. AC Test Load

(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)

Figure 1. AC Test Load

*Including jig and scope capacitance.

DC Electrical Characteristics(1)

(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V)

AC Test Conditions

Capacitance

(TA = +25°C, f = 1.0MHz, SOJ package)

DC Electrical Characteristics

(VCC = 5.0V ± 10%)

2948 drw 03

480

Ω

255

Ω

30pF*

DATA OUT

2948 drw 04

480

Ω

255

Ω

5pF*

DATA OUT

Symbol

Parameter

Test Conditions

IDT71256SA

Unit

Min.

Max.

|ILI|

Input Leakage Current

VCC = Max., VIN = GND to VCC

___

5µ A

|ILO|

Output Leakage Current

VCC = Max.,

CS = VIH, VOUT = GND to VCC

___

5µ A

VOL

Output Low Voltage

IOL = 8mA, VCC = Min.

___

0.4

VOH

Output High Voltage

IOH = -4mA, VCC = Min.

2.4

___

2948 tbl 05

NOTES:

1. All values are maximum guaranteed values.

2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.

Symbol

Parameter

71256SA12

71256SA15

71256SA20

71256SA25

Unit

ICC

Dynamic Operating Current

CS < VIL, Outputs Open, VCC = Max., f = fMAX(2)

160

150

145

ISB

Standby Power Supply Current (TTL Level)

CS > VIH, Outputs Open, VCC = Max., f = fMAX(2)

ISB1

Standby Power Supply Current (CMOS Level)

CS > VHC, Outputs Open, VCC = Max., f = 0(2),

VIN < VLC or VIN > VHC

2948 tbl 06

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

AC Test Load

GND to 3.0V

3ns

1.5V

See Figures 1 and 2

2948 tbl 07

NOTE:

1. This parameter is guaranteed by device characterization, but not production

tested.

Symbol

Parameter(1)

Conditions

Max.

Unit

CIN

Input Capacitance

VIN = 3dV

CI/O

I/O Capacitance

VOUT = 3dV

2948 tbl 08

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