IDT7132LA55P datasheet(4/11 Pages) IDT

4 / 11 page

IDT7132SA/LA AND IDT7142SA/LA

HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.02

1250

Ω

30pF*

775

Ω

DATA OUT

1250

Ω

775

Ω

5pF*

DATA OUT

2692 drw 06

100pF for 55 and 100ns versions

270

Ω

30pF*

BUSY or INT

100pF for 55 and 100ns versions

DATA RETENTION WAVEFORM

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

2692 tbl 07

GND TO 3.0V

5ns

1.5V

Figures 1, 2, and 3

DATA RETENTION CHARACTERISTICS (LA Version Only)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VDR

VCC for Data Retention

2.0

—

ICCDR

Data Retention Current

VCC = 2.0V,

CE ≥ VCC -0.2V

Mil.

—

100

4000

µA

VIN

≥ VCC -0.2V or VIN ≤ 0.2V Com’l.

—

100

1500

µA

tCDR

Chip Deselect to Data

—

Retention Time

Operation Recovery

tRC

——

Time

(3)

(2)

lDT7132LA/IDT7142LA

Figure 2. Output Test Load

(for tHZ, tLZ, tWZ, and tOW)

* Including scope and jig

Figure 1. AC Output Test Load

2692 tbl 06

NOTES:

1. VCC = 2V, TA = +25

°C, and is not production tested.

2. tRC = Read Cycle Time

3. This parameter is guaranteed but not production tested.

VCC

4.5V

DATA RETENTION MODE

tCDR

VIH

VDR

VDR 2.0V

2692 drw 05

≥

Figure 3.

BUSY

BUSY and INT

INT

AC Output Test Load

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