IDT74FCT573TP datasheet(7/8 Pages) IDT

7 / 8 page

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT

FAST CMOS OCTAL TRANSPARENT LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.12

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

SWITCH POSITION

ENABLE AND DISABLE TIMES

PROPAGATION DELAY

Pulse

Generator

R T

D.U.T.

V CC

VIN

C L

VOUT

50pF

500

Ω

500

Ω

7.0V

1.5V

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

tSU

tREM

tSU

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

1.5V

SAME PHASE

INPUT TRANSITION

1.5V

VOH

tPLH

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

1.5V

tPLH

tPHL

VOL

CONTROL

INPUT

1.5V

3.5V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH

CLOSED

SWITCH

OPEN

VOL

0.3V

tPLZ

tPZL

tPZH

tPHZ

3.5V

1.5V

ENABLE

DISABLE

VOH

PRESET

CLEAR

CLOCK ENABLE

ETC.

Test

Switch

Disable Low

Enable Low

Closed

All Other Tests

Open

Open Drain

DEFINITIONS:

CL=

Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

2564 lnk 13

2564 drw 09

2564 drw 10

2564 drw 11

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-

HIGH

2. Pulse Generator for All Pulses: Rate

≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

2564 drw 13

2564 drw 12

IDT74FCT573TP Datasheet(PDF) 7 Page - Integrated Device Technology

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