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IA80C152

Preliminary Data Sheet

UNIVERSAL COMMUNICATIONS CONTROLLER

Copyright

© 2000

[_________The End of Obsolescence

™

Table 2 - I/O Signal Descriptions

Signal Name

Description

P4.3

P4.4

P4.5

P4.6

P4.7

use a port signal as an output, a 1 or 0 written to the port location is

presented at the output.

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

Port 5 - 8-bit bi-directional port that is NOT bit addressable. To use

the port as an input, write a 1 to the port location. Internal pull-ups

pull the input high and source current when the input is driven low.

To use the port as an output, 1s or 0s written to the port are

presented at the output.

This port also provides the low-byte of the multiplexed address and

data bus depending on the state of !EBEN.

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

Port 6 - 8-bit bi-directional port that is NOT bit addressable. To use

the port as an input, write a 1 to the port location. Internal pull-ups

pull the input high and source current when the input is driven low.

To use the port as an output, 1s or 0s written to the port are

presented at the output.

This port also provides the high-byte of the multiplexed address and

data bus depending on the state of !EBEN.

VCC

Supply Voltage

VSS

Device Ground

XTAL1

Input to the internal clock generator

XTAL2

Output from the internal oscillator amplifier

Memory Space

Memory space is divided up into program and data memory. Program memory is all external to the

IA80C152. Data memory is divided up into external and internal data memory. There can be up to

64K bytes of external program and data memory. Internal data memory is 256 bytes that is

mapped between RAM, SFRs, and Register Banks. Figure 5 diagrams the organization of the

IA80C152 memory space. See the C8051 section for further details.

Program memory is accessed using control signals and ports. On the JA and JC versions of the

IA80C152 this access is performed through ports P0 and P2. Further, since there is no internal

ROM, the entire program memory space is accessed via ports P0 and P2. On the JB and JD

version of the IA80C152, program memory access can be through either ports P0 and P2, or ports

P5 and P6. Which set of ports program memory fetches are made is controlled by the input signals

!EA and !EBEN. Table 3 summarizes the IA80C152 versions and the relationship to program

memory fetches.