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80960HT Datasheet(PDF) 63 Page - Intel Corporation |
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80960HT Datasheet(HTML) 63 Page - Intel Corporation |
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63 / 102 page ![]() 80960HA/HD/HT Advance Information Datasheet 57 Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ADS SUP,CT3:0, W/R BLAST DT/R DEN A3:2 WAIT D31:0, CLKIN A2 1 D 1 D 1 D 1 D 1 A Valid A3:2 = 00, 01, 10 or 11 D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 D7:0 Byte 3 D/C,LOCK, A31:4 BE1/A1, A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 =11 BE0/A0 DP3:0 PCHK Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 Enabled 1 OFF 0 1 0001 8-Bit X x Enabled 1 X xx X xxxxx 1 01 Disabled 0 2 00010 Function Bit Value External Ready Control Pipe- Lining Parity Enable NRAD NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 00 PMCON |
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