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83C51KB Datasheet(PDF) 15 Page - Intel Corporation |
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83C51KB Datasheet(HTML) 15 Page - Intel Corporation |
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15 / 19 page ![]() 15 83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER Figure 5. External Clock Drive ICC Power Supply Current: Active Mode at 6MHz Idle Mode at 6MHz Power Down Mode 7 2 10 12 5 50 mA mA µA RST, EA# to VCC RST, EA# to VSS RST, EA# to VSS (RCIN pin to external resis- tor, all other pins are no connect) VPOR Power on reset crossover 2.4 3 3.6 V Table 7. D.C. Characteristics (Continued) Symbol Parameter Min Typical (note 1) Max Unit Test Condition NOTE: 1. Typical values are obtained using VCC=5.0V, TA=25°C and are not guaranteed. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follow: Maximum IOL per Port Pin—Port 0, 1, 2, P3.1-P3.3: 10mA Maximum IOL per Port Pin—P3.4-P3.7: 22mA Maximum IOL per 8-bit port—Port 0-2: 15mA Ports 3: 95mA Maximum Total IOL for AllOutput Pins: 110mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance dis- charging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic. 4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the address lines are stabilizing. 0.7 V CC A4252-01 0.45 V V CC – 0.5 0.2 V CC – 0.1 TCHCL TCLCX TCLCL TCLCH TCHCX |
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