AUTOMOTIVE 87C196KC

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Figure 1 87C196KC Block Diagram

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Figure 2 The 87C196KC Family Nomenclature

87C196KC Enhanced Feature Set over the 87C196KB

1 The 87C196KC has twice the RAM and twice the EPROM of the 87C196KB Also a Vertical Register

Windowing Scheme allows the extra 256 bytes of RAM to be used as registers This greatly reduces the

context switching time

2 Peripheral Transaction Server (PTS) The PTS is an alternative way to service an interrupt reducing latency

and overhead Each interrupt can be mapped to its PTS channel which acts like a DMA channel Each

interrupt can now do a single or block transfer without executing an Interrupt service routine Special PTS

modes exist for the AD converter HSI and HSO

3 Two extra Pulse Width Modulated outputs The 87C196KC has added 2 PWM outputs that are functionally

compatible to the 87C196KB PWM

4 Timer2 Internal Clocking Timer2 can now be clocked with an internal source every 1 or 8 state times

5 The AD can now perform an 8- as well as a 10-bit conversion 8-bit conversion allows for a faster

conversion time

6 Additional On-chip Memory Security Two UPROM (Uneraseable Programmable Read Only Memory) bits

can be programmed to disable the bus controller for external code and data fetches Once programmed a

UPROM bit cannot be erased By shutting off the bus controller for external fetches no one can try and

gain access to your code by executing from external memory

7 New Instructions The 87C196KC has 5 new instructions An exchange (XCHBXCHW) instruction swaps

two memory locations an Interruptable Block Move Instruction (BMOVI) a Table Indirect Jump (TIJMP)

instruction and two instructions for enabling and disabling the PTS (EPTSDPTS)

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