AUTOMOTIVE 87C196KD

PIN DESCRIPTIONS

Symbol

Name and Function

Main supply voltage (5V)

portion of the AD converter and the logic used to read Port 0 Must be connected for AD

and Port 0 to function

ANGND

Reference ground for the AD converter Must be held at nominally the same potential as

Timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to

is the programming voltage on the EPROM device

XTAL1

Input of the oscillator inverter and of the internal clock generator

XTAL2

Output of the oscillator inverter

CLKOUT

Output of the internal clock generator The frequency of CLKOUT is

the oscillator

frequency

RESET

Reset input to the chip

BUSWIDTH

Input for buswidth selection If CCR bit 1 is a one this pin selects the bus width for the bus

cycle in progress If BUSWIDTH is a 1 a 16-bit bus cycle occurs If BUSWIDTH isa0an

8-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus

NMI

A positive transition causes a vector through 203EH

INST

Output high during an external memory read indicates the read is an instruction fetch INST

is valid throughout the bus cycle INST is activated only during external memory accesses

and output low for a data fetch

EA

Input for memory select (External Access) EA equal to a TTL-high causes memory

accesses to locations 2000H through 5FFFH to be directed to on-chip ROMEPROM EA

equal to a TTL-low causes accesses to those locations to be directed to off-chip memory

ALEADV

Address Latch Enable or Address Valid output as selected by CCR Both pin options

provide a signal to demultiplex the address from the addressdata bus When the pin is

ADV it goes inactive high at the end of the bus cycle ALEADV is activated only during

external memory accesses

RD

Read signal output to external memory RD is activated only during external memory reads

WR WRL

Write and Write Low output to external memory as selected by the CCR WR will go low for

every external write while WRL will go low only for external writes where an even byte is

being written WR WRL is activated only during external memory writes

BHE WRH

Bus High Enable or Write High output to external memory as selected by the CCR BHE e

0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0

selects the bank of memory that is connected to the low byte of the data bus Thus

accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the

high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is

selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH

is valid only during 16-bit external memory write cycles

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