IDT29FCT52AT/BT/CT/DT, IDT29FCT/2052AT/BT/CT, IDT29FCT53AT/BT/CT

FAST CMOS OCTAL REGISTERED TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.1

2

PIN CONFIGURATIONS

5

6

7

8

9

10

11

12

GND

1

2

3

4

24

23

22

21

20

19

18

17

Vcc

16

15

14

13

P24-1

D24-1

SO24-2

SO24-7*

SO24-8*

&

E24-1

CEB

CEA

CPB

CPA

OEA

B

0

OEB

2629 drw 02

5

6

7

8

9

10

11

L28-1

25

24

23

22

21

20

19

12 13 14 15 16 17 18

43

2

1

28 27 26

INDEX

2629 drw 03

OEB

NC

NC

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

LCC

TOP VIEW

* For 29FCT52/29FCT2052AT/BT/CT only

PIN DESCRIPTION

Name

I/O

Description

I/O

Eight bidirectional lines carrying the A Register inputs or B Register outputs.

I/O

Eight bidirectional lines carrying the B Register inputs or A Register outputs.

CPA

I

Clock for the A Register. When

CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of

the CPA signal.

CEA

I

Clock Enable for the A Register. When

CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition

of the CPA signal. When

CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions.

OEB

I

Output Enable for the A Register. When

CPB

I

Clock for the B Register. When

CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of

the CPB signal.

CEB

I

Clock Enable for the B Register. When

CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition

of the CPB signal. When

CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions.

OEA

I

Output Enable for the B Register. When

2629 tbl 01