P87C511 datasheet(6/21 Pages) INTEL

6 / 21 page

87C5180C51BH80C31BH

IDLE MODE

In Idle Mode the CPU puts itself to sleep while all

the on-chip peripherals remain active The mode is

invoked by software The content of the on-chip

RAM and all the Special Functions Registers remain

unchanged during this mode The Idle Mode can be

terminated by any enabled interrupt or by a hard-

ware reset

It should be noted that when Idle is terminated by a

hardware reset the device normally resumes pro-

gram execution from where it left off up to two ma-

chine cycles before the internal reset algorithm

takes control On-chip hardware inhibits access to

internal RAM in this event but access to the port

pins is not inhibited To eliminate the possibility of an

unexpected write to a port pin when Idle is terminat-

ed by reset the instruction following the one that

invokes Idle should not be one that writes to a port

pin or to external memory

POWER DOWN MODE

To save even more power a Power Down mode can

be invoked by software In this mode the oscillator

is stopped and the instruction that invoked Power

Down is the last instruction executed The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is transmitted

On the 87C51BH either a hardware reset or an ex-

ternal interrupt can cause an exit from Power Down

Reset redefines all the SFR’s but does not change

the on-chip RAM An external interrupt allows both

the SFRs and on-chip RAM to retain their values

To properly terminate Power Down the reset or ex-

ternal interrupt should not be executed before VCC is

restored to its normal operating level and must be

held active long enough for the oscillator to restart

and stabilize (normally less than 10 ms)

With an external interrupt INT0 and INT1 must be

enabled and configured as level-sensitive Holding

the pin low restarts the oscillator but bringing the pin

back high completes the exit Once the interrupt is

serviced the next instruction to be executed after

RET1 will be the one following the instruction that

put the device into Power Down

DESIGN CONSIDERATIONS

Exposure to light when the device is in operation

may cause logic errors For this reason it is sug-

gested that an opaque label be placed over the

window when the die is exposed to ambient light

The 87C51BH now have some additional fea-

tures The features are asynchronous port reset

4 interrupt priority levels power off flag ALE dis-

able serial port automatic address recognition

serial port framing error detection 64-byte en-

cryption array and 3 program lock bits These

features cannot be used with the older versions

of 80C51BH80C31BH The newer version of

80C51BH80C31BH will have change identifier

‘‘A’’ appended to the lot number

Table 2 Status of the External Pins during Idle and Power Down

Mode

Program

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Memory

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power Down

Internal

Data

Power Down

External

Float

Data

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