AD5530 datasheet(13/20 Pages) AD

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AD5530/AD5531

Rev. B | Page 13 of 20

THEORY OF OPERATION

SDO

LDAC

12-/14-BIT DAC

DAC REGISTER

SYNC REGISTER

16-BIT SHIFT

SYNC

SDIN

REFIN

OUTPUT

DAC ARCHITECTURE

The AD5530/AD5531 are pin-compatible 12- and 14-bit DACs.

The AD5530 consists of a straight 12-bit R-2R voltage mode

DAC, and the AD5531 consists of a 14-bit R-2R section. Using a

5 V reference connected to the REFIN pin and REFAGND tied

to 0 V, a bipolar ±10 V voltage output results. The DAC coding

is straight binary.

SERIAL INTERFACE

Serial data on the SDIN input is loaded to the input register

under the control of SCLK, SYNC

LDAC

, and

. A write

operation transfers a 16-bit word to the AD5530/AD5531.

Figure 2 and Figure 3 show the timing diagrams. Figure 18 and

Figure 20. Simplified Serial Interface

Figure 19 show the contents of the input shift register. Twelve or

14 bits of the serial word are data bits; the rest are don’t cares.

Data written to the part via SDIN is available on the SDO pin 16

clocks later if the readback function is not used. SDO data is

clocked out on the falling edge of the serial clock with some delay.

DB15 (MSB)

D10

D11

D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

DB0 (LSB)

DATA BITS

PD FUNCTION

Figure 18. AD5530 Input Shift Register Contents

The

pin allows the user to place the device into power-down

mode. While in this mode, power consumption is at a minimum;

the device draws only 50 μA of current. The

D11

D12

D13

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DB15 (MSB)

DB0 (LSB)

DATA BITS

PD function does

not affect the contents of the DAC register.

Figure 19. AD5531 Input Shift Register Contents

READBACK FUNCTION

SYNC

The serial word is framed by the signal,

. After a high-to-

low transition on

The AD5530/AD5531 allows the data contained in the DAC

SYNC, data is latched into the input shift

DAC register and output can be updated. The LDAC signal is

examined on the falling edge of SYNC; depending on its status,

either a synchronous or asynchronous update is selected. If

LDAC is low, then the DAC register and output are updated on

the low-to-high transition of SYNC. Alternatively, if LDAC is

high upon sampling, the DAC register is not loaded with the

new data on a rising edge of SYNC. The contents of the DAC

low any time after the 16-bit data transfer is complete. LDAC

can be tied permanently low if required. A simplified diagram

of the input loading circuitry is illustrated in Figure 20.

RBEN

and SDO (serial data out). When

is taken low, on

the next falling edge of SCLK, the contents of the DAC register

are transferred to the shift register. RBEN can be used to frame

the readback data by leaving it low for 16 clock cycles, or it can

be asserted high after the required hold time. The shift register

contains the DAC register data and this is shifted out on the

SDO line on each falling edge of SCLK with some delay. This

ensures the data on the serial data output pin is valid for the

falling edge of the receiving part. The two MSBs of the 16-bit

word are 0s.

CLR FUNCTION

The falling edge of CLR causes VOUT to be reset to the same

potential as DUTGND. The contents of the registers remain

unchanged, so the user can reload the previous data with LDAC

after CLR is asserted high. Alternatively, if LDAC is tied low, the

output is loaded with the contents of the DAC register auto-

matically after CLR is brought high.

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