M80C86M80C86-2

MAXIMUM MODE

(Continued)

271058 – 10

NOTES

1 All timing measurements are made at 15V

3 Cascade address is valid between first and second INTA cycle

4 Two INTA cycles run back-to-back The M80C86 local ADDRDATA BUS is floating during both INTA cycles Control for

pointer address is shown for second INTA cycle

5 Signals at M82C84A or M82C88 are shown for reference only

6 The issuance of the M82C88 command and control signals (MRDC MWTC AMWC IORC IOWC AIOWC INTA and

DEN) lags the active high M82C88 CEN

17