M82C288

Table 1 Pin Description

(Continued)

Symbol

Type

Name and Function

INTA

O

INTERRUPT ACKNOWLEDGE

tells an interrupting device that its interrupt request

is being acknowledged This command output is active LOW The MB and CMDLY

inputs control when this output becomes active READY controls when it becomes

inactive

System Power a

5V Power Supply

GND

System Ground

0V

Table 2 Command and Control Outputs for Each Type of Bus Cycle

Type of

MIO

S1

S0

Command

DTR

ALE DEN

MCE

Bus Cycle

Activated

State

Issued

Issued

Interrupt Acknowledge

0

0

0

INTA

LOW

YES

YES

IO Read

0

0

1

IORC

LOW

YES

NO

IO Write

0

1

0

IOWC

HIGH

YES

NO

None Idle

0

1

1

None

HIGH

NO

NO

HaltShutdown

1

0

0

None

HIGH

NO

NO

Memory Read

1

0

1

MRDC

LOW

YES

NO

Memory Write

1

1

0

MWTC

HIGH

YES

NO

None Idle

1

1

1

None

HIGH

NO

NO

Operating Modes

Two types of buses are supported by the M82C288

MULTIBUS I and non-MULTIBUS I When the MB

input is strapped HIGH MULTIBUS I timing is used

In MULTIBUS I mode the M82C288 delays com-

mand and data activation to meet IEEE-796 require-

ments on address to command active and write data

to command active setup timing MULTIBUS I mode

requires at least one wait state in the bus cycle since

the command outputs are delayed

The non-

MULTIBUS I mode does not delay any outputs and

does not require wait states The MB input affects

the timing of the command and DEN outputs

Command and Control Outputs

The type of bus cycle performed by the local bus

master is encoded in the MIO S1 and S0 inputs

Different command and control outputs are activat-

ed depending on the type of bus cycle Table 2 indi-

cates the cycle decode done by the M82C288 and

the effect on command DTR ALE DEN and MCE

outputs

Bus cycles come in three forms read write and

halt Read bus cycles include memory read IO

read and interrupt acknowledge The timing of the

associated read command outputs (MRDC IORC

and INTA) control outputs (ALE DEN DTR) and

control inputs (CENAEN CENL CMDLY MB and

READY) are identical for all read bus cycles Read

cycles differ only in which command output is acti-

vated The MCE control output is only asserted dur-

ing interrupt acknowledge cycles

Write bus cycles activate different control and com-

mand outputs with different timing than read bus cy-

cles Memory write and IO write are write bus cy-

cles whose timing for command outputs (MWTC and

IOWC) control outputs (ALE DEN DTR) and con-

trol inputs (CENAEN

CENL

CMDLY

MB and

READY) are identical They differ only in which com-

mand output is activated

Halt bus cycles are different because no command

or control output is activated All control inputs are

ignored until the next bus cycle is started via S1 and

S0

Static Operation

All M82C288 circuitry is of static design Internal reg-

isters and logic are static and require no refresh as

with dynamic circuit design This eliminates the mini-

mum operating frequency restriction placed on the

HMOS M82288 The CHMOS III M82C288 can oper-

ate from DC to the appropriate upper frequency limit

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