CS82C237 datasheet(17/25 Pages) INTERSIL

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4-164

Figure 9 shows the data bus for a 16-bit DMA application

with the 82C237. High memory and low memory are

selected accordingly with A0 and the 8/16 signal during DMA

transfers. The 8/16 signal is formed from DWLE with a D ﬂip-

ﬂop and ADSTB. ADSTB must be inverted to the D ﬂip-ﬂop

since DWLE is set up to the falling edge of ADSTB and the

74F74 latches data on the rising edge of CLK.

The ADSTB inverted could be eliminated by using a 74F75

falling edge D latch. The latch on D8-D15 is needed for 16-

bit memory-to-memory transfers. The upper eight bits of

data are latched by MEMR during the read half of the trans-

fer. The data is then enabled onto the data bus during the

write half of the transfer.

FIGURE 9. DATA BUS FOR 16-BIT DMA APPLICATION

NOTE: Only needed for memory-to-memory transfers.

HLDA

MEMCS

FROM DECODER

8/16

STB

LATCH

HIGH

D8-D15

I/O

TRANSCEIVER

DEVICE

D0 - D7

MEMORY

I/O

DEVICE

LOW

MEMORY

TRANSCEIVER

IOR

IOW

MEMR

MEMW

82C237

DWLE

ADSTB

D0-D7

VCC

CLK

74F74

80C286

D8-D15

D0-D7

(SEE NOTE)

82C237

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