82C50 datasheet(13/21 Pages) INTERSIL

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Transmitter

The serial transmitter section consists of a Transmitter Hold-

ing Register (THR), Transmitter Shift Register (TSR), and

associated control logic. The Transmitter Holding Register

Empty (THRE) and Transmitter Shift Register Empty (TEMT)

are two bits in the Line Status Register which indicate the

status of THR and TSR. To transmit a 5-8 bit word, the word

is written through D0-D7 to the THR. The microprocessor

should perform a write operation only if THRE is high. The

THRE is set high when the word is automatically transferred

from the THR to the TSR during the transmission of the start

bit.

When the transmitter is idle, both THRE and TEMT are high.

The ﬁrst word written causes THRE to be reset to 0. After

completion of the transfer, THRE returns high. TEMT

remains low for at least the duration of the transmission of

the data word. If a second character is transmitted to the

THR, the THRE is reset low. Since the data word cannot be

transferred from the THR to the TSR until the TSR is empty,

THRE remains low until the TSR has completed transmis-

sion of the word. When the last word has been transmitted

out of the TSR, TEMT is set high. THRE is set high one THR

to TSR transfer time later.

Receiver

Serial asynchronous data is input into the SIN pin. The idle

state of the line providing the input into SIN is high. A start

bit detect circuit continually searches for a high to low transi-

tion from the idle state. When the transition is detected, a

counter is reset, and counts the 16X clock to 7 1/2, which is

the center of the start bit. The start bit is valid if the SIN is

still low at the mid bit sample of the start bit. Verifying the

start bit prevents the receiver from assembling an incorrect

data character due to a low going noise spike on the SIN

input.

The Line Control Register determines the number of data

bits in a character (LCR(0), LCR(1)), number of stop bits

LCR(2), if parity is used LCR(3), and the polarity of parity

LCR(4). Status information for the receiver is provided in the

Line Status Register. When a character is transferred from

the Receiver Shift Register to the Receiver Buffer Register,

the Data Received indication in LSR(0) is set high. The CPU

reads the Receiver Buffer Register through D0-D7. This read

resets LSR(0). If D0-D7 are not read prior to a new character

transfer from the RSR to the RBR, the overrun error status

indication is set in LSR(1). The parity check tests for even or

odd parity on the parity bit, which precedes the ﬁrst stop bit.

If there is a parity error, the parity error is set in LSR (2).

There is circuitry which tests whether the stop bit is high. If it

is not, a framing error indication is generated in LSR(3).

The center of the start bit is deﬁned as clock count 7 1/2. If

the data into SIN is a symmetrical square wave, the center of

the data cells will occur within

±3.125% of the actual center,

providing an error margin of 46.875%. The start bit can

begin as much as one 16X clock cycle prior to being

detected.

Baud Rate Generator (BRG)

The BRG generates the clocking for the UART function,

providing standard ANSI/CCITT bit rates. The oscillator

driving the BRG may be provided either with the addition of

an external crystal to the XTAL1 and XTAL2 inputs, or an

external clock into XTAL1. In either case, a buffered clock

output, BAUDOUT, is provided for other system clocking. If

two 82C50As are used on the same board, one can use a

crystal, and the buffered clock output can be routed directly

into the XTAL1 of the second 82C50A.

The data rate is determined by the Divisor Latch registers

DLL and DLM and the external frequency or crystal input,

with the BAUDOUT providing an output 16X the data rate.

The bit rate is selected by programming the two divisor

latches, Divisor Latch Most Signiﬁcant Byte and Divisor

Latch Least Signiﬁcant Byte. Setting DLL = 1 and DLM = 0

selects the divisor to divide by 1 (divide by 1 gives maximum

baud rate for a given input frequency at XTAL1). The on-chip

oscillator is optimized for a 10MHz crystal. Usually, higher

frequency are less expensive than lower frequency crystals.

The BRG can use any of three different popular crystals to

provide standard baud rates. The frequency of these three

common

crystals

the

market

are

1.8432MHz,

2.4576MHz, and 3.072MHz. With these standard crystals,

standard bit rates from 50 to 38.5kbps are available. The fol-

lowing tables illustrate the divisors needed to obtain

standard rates using these three crystal frequencies.

TABLE 4. BAUD RATES USING 1.8432MHz CRYSTAL

DESIRED

BAUD

RATE

DIVISOR USED TO

GENERATE

16 x CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

2304

1536

110

1047

0.026

134.5

857

0.058

150

768

300

384

600

192

1200

1800

2000

0.69

2400

3600

4800

7200

9600

19200

38400

56000

2.86

82C50A

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