4-334

Functional Diagram

Pin Description

PIN

SYMBOL

NUMBER

TYPE

DESCRIPTION

20

GND

10

GROUND.

S0, S1, S2

19, 3, 18

I

STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors.

The 82C88 decodes these inputs to generate command and control signals at the appropriate time.

When Status pins are not in use (passive), command outputs are held HIGH (See Table1).

CLK

2

I

CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock

generator and serves to establish when command/control signals are generated.

ALE

5

O

ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This sig-

nal is active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use

with transparent D type latches, such as the 82C82 and 82C83H.

DEN

16

O

DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus.

This signal is active HIGH.

DT/R

4

O

DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers.

A HIGH on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from

I/O or memory).

AEN

6

I

ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns

(250ns maximum) after it becomes active (LOW). AEN going inactive immediately three-states the com-

mand output drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode

(IOB tied HIGH).

CEN

15

I

COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN con-

trol outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.

IOB

1

I

INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus

mode. When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System

Bus sections).

GND

COMMAND

SIGNALS

CONTROL

INPUT

IOB

CEN

CLK

AEN

CONTROL

SIGNAL

GENERATOR

DEN

ALE

DT/R

MCE/PDEN

COMMAND

SIGNAL

GENERATOR

AIOWC

IOWC

AMWC

MWTC

MRDC

IORC

S2

S1

S0

INTA

ADDRESS LATCH,

DATA TRANSCEIVER,

AND INTERRUPT

CONTROL SIGNALS

CONTROL

LOGIC

STATUS

DECODER

82C88

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