4-344

Functional Diagram

Pin Description

PIN

SYMBOL

NUMBER

TYPE

DESCRIPTION

20

decoupling.

GND

10

GROUND.

S0, S1, S2

1, 18-19

I

STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The

82C89 decodes these pins to initiate bus request and surrender actions. (See Table 1).

CLK

17

I

CLOCK: From the 82C84A or 82C85 clock chip and serves to establish when bus arbiter actions

are initiated.

LOCK

16

I

LOCK: A processor generated signal which when activated (low) prevents the arbiter from surren-

dering the multi-master system bus to any other bus arbiter, regardless of its priority.

CRQLCK

15

I

COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the

multi-master system bus to any other bus arbiter requesting the bus through the CBRQ input pin.

RESB

4

I

RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a

multi-master system bus and a Resident Bus. Strapped high, the multi-master system bus is re-

quested or surrendered as a function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB

input is ignored.

ANYRQST

14

I

ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered

to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter

requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible).

When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Informa-

tion. If ANYRQST is strapped high and CBRQ is activated, the bus is surrendered at the end of

the present bus cycle. Strapping CBRQ low and ANYRQST high forces the 82C89 arbiter to sur-

render the multi-master system bus after each transfer cycle. Note that when surrender occurs

BREQ is driven false (high).

CONTROL

ARBITRATION

MULTIBUS

INTERFACE

LOCAL

BUS

INTERFACE

+5V

GND

CONTROL/

STRAPPING

OPTIONS

80C86/

80C88

STATUS

COMMAND

SIGNALS

SYSTEM

SIGNALS

BPRN

SYSB/

RESB

INIT

BCLK

BREQ

BPRO

BUSY

CBRQ

AEN

CLK

RESB

ANYRQST

LOCK

S 1

IOB

CRQLCK

S 0

S 2

STATUS

DECODER

82C89