4-282

Functional Diagram

Gated Inputs

During normal system operation of a latch, signals on the

bus at the device inputs will become high impedance or

make transitions unrelated to the operation of the latch.

These unrelated input transitions switch the input circuitry

and typically cause an increase in power dissipation in

CMOS devices by creating a low resistance path between

ing threshold. Additionally, if the driving signal becomes high

impedance (``float'' condition), it could create an indetermi-

nate logic state at the inputs and cause a disruption in

device operation.

The Intersil 82C8X series of bus drivers eliminates these

conditions by turning off data inputs when data is latched

(STB = logic zero for the 82C82/83H) and when the device is

disabled (OE = logic one for the 82C86H/87H). These gated

ground power supply pins by turning off the upper P-channel

and lower N-channel (See Figures 1 and 2). No current flow

logic states from floating inputs are not transmitted. The next

stage is held to a valid logic level internal to the device.

D.C. input voltage levels can also cause an increase in ICC if

cuitry in its linear operating region (partially conducting

state). The 82C8X series gated inputs mean that this condi-

tion will occur only during the time the device is in the trans-

parent mode (STB = logic one). ICC remains below the

maximum ICC standby specification of 10

µA during the time

inputs are disabled, thereby greatly reducing the average

power dissipation of the 82C8X series devices.

Decoupling Capacitors

The transient current required to charge and discharge the

300pF load capacitance specified in the 82C83H data sheet

is determined by

Assuming that all outputs change state at the same time and

that dv/dt is constant;

puts.

This current spike may cause a large negative voltage spike on

ter out this noise, it is recommended that a 0.1

µF ceramic disc

with placement being as near to the device as possible.

DI0

DI1

DI2

DI3

DI4

DI5

DI6

DI7

STB

DO0

DO1

DO2

DO3

DO4

DO5

DO6

DO7

OE

DQ

CLK

P

P

N

N

N

P

INTERNAL

DATA

STB

DATA IN

FIGURE 1. 82C82/83H

N

N

P

P

P

N

DATA

INTERNAL

OE

DATA IN

FIGURE 2. 82C86H/87H GATED INPUTS

IC

L

V

CC

80 percent

×

()

t

⁄

--------------------------------------------------------

=

(EQ. 1)

P

P

N

N

N

P

INTERNAL

DATA

STB

DATA IN

ADDRESS

ADDRESS

ALE

MULTI-

ICC

PLEXED

BUS

FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS

82C83H