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ACS161K Datasheet(PDF) 1 Page - Intersil Corporation |
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ACS161K Datasheet(HTML) 1 Page - Intersil Corporation |
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1 / 4 page  1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962F9670601VEC -55oC to +125oC MIL-PRF-38535 Class V 16 Lead SBDIP 5962F9670601VXC -55oC to +125oC MIL-PRF-38535 Class V 16 Lead Ceramic Flatpack ACS161D/Sample 25oC Sample 16 Lead SBDIP ACS161K/Sample 25oC Sample 16 Lead Ceramic Flatpack ACS161HMSR 25oC Die Die ACS161MS Radiation Hardened 4-Bit Synchronous Counter January 1996 Pinouts 16 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835, DESIGNATOR CDIP2-T16, LEAD FINISH C TOP VIEW 16 PIN CERAMIC FLATPACK MIL-STD-1835, DESIGNATOR CDFP4-F16, LEAD FINISH C TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CP P0 P1 P2 P3 GND PE VCC Q0 Q1 Q2 Q3 TE SPE TC MR 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 MR CP P0 P1 P2 P3 PE GND VCC TC Q0 Q1 Q2 Q3 TE SPE Features • Devices QML Qualified in Accordance with MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96706 and Intersil’ QM Plan • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) • Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ) • SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg • Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse • Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V • Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min • Input Current ≤ 1µA at VOL, VOH • Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ) Description The Intersil ACS161MS is a Radiation Hardened 4-Bit Binary Synchronous Counter. The MR is an active low master reset. SPE is an active low Synchronous Parallel Enable which disables counting and allows data at the preset inputs (P0 - P3) to load the counter. CP is the positive edge clock. TC is the terminal count or carry output. Both TE and PE must be high for counting to occur, but are irrelevant to loading. TE low will keep TC low. The ACS161MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic family. The ACS161MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix). Spec Number 518818 File Number 3600.1 |
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Similar Description - ACS161K |
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