4-9

Allowable Input Bandwidth

(Note 4)

-

25

MHz

-3dB Input Bandwidth

-

40

-

MHz

REFERENCE INPUTS

Input Range

(Note 4)

-

(Note 4)

V

Input Loading

Resistor Ladder Impedance

640

-

960

Ω

DIGITAL INPUTS

Digital Input

CLOCK

(Notes 3, 4)

-

-

V

CE1, CE2

(Note 4)

-

-

V

CLOCK

(Notes 3, 4)

--

V

CE1, CE2

(Note 4)

--

V

Input Leakage, Except CLK

V = 0V, 5V

-

-

±1

µA

Input Leakage, CLK

(Note 3)

-

±100

±150

µA

DIGITAL OUTPUTS

Digital Outputs

Output Low (Sink) Current

6

-

-

mA

Output High (Source) Current

-3

-

-

mA

Three-State Leakage Current

-

±0.2

±5

µA

TIMING CHARACTERISTICS

Conversion Timing

Maximum Conversion Speed

CLK = Square Wave

25

35

-

MSPS

Auto-Balance Time (

20

-

-

ns

Sample Time (

20

-

5000

ns

Output Timing

Data Valid Delay

(Note 4)

-

30

40

ns

Data Hold Time

(Note 4)

15

25

-

ns

Output Enable Time

-

15

-

ns

Output Disable Time

-

10

-

ns

POWER SUPPLY CHARACTERISTICS

Continuous Clock

-

5.5

-

mA

Continuous

-

0.4

-

mA

Continuous

2

-

mA

Continuous Clock

-

1.5

-

mA

Continuous

5

10

mA

Continuous

5

20

mA

NOTES:

however.

2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and VDD

voltage.

3. The CLK input is a CMOS inverter with a 50k

4. Parameter not tested, but guaranteed by design or characterization.

Electrical Specifications

Unless Otherwise Specified (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

CA3304, CA3304A