7-1327

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

CD40106BMS

CMOS Hex Schmitt Triggers

Features

• High Voltage Type (20V Rating)

• Schmitt Trigger Action with No External Components

• Hysteresis Voltage (Typ.)

- 0.9V at VDD = 5V

-

2.3V at VDD = 10V

- 3.5V at VDD = 15V

• Noise Immunity Greater than 50%

• No Limit on Input Rise and Fall Times

• Low VDD to VSS Current During Slow Input Ramp

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Standardized Symmetrical Output Characteristics

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Wave and Pulse Shapers

• High Noise Environment Systems

• Monostable Multivibrators

• Astable Multivibrators

Description

CD40106BMS consists of six Schmitt trigger circuits. Each

circuit functions as an inverter with Schmitt trigger action on

the input. The trigger switches at different points for positive

and negative going signals. The difference between the

positive going voltage (VP) and the negative going voltage

(VN) is defined as hysteresis voltage (VH) (see Figure 17).

The CD40106BMS is supplied in these 14 lead outline

packages:

Braze Seal DIP

H4Q

Frit Seal DIP

H1B

Ceramic Flatpack

H3W

December 1992

File Number

3354

Pinout

CD40106BMS

TOP VIEW

Functional Diagram

Logic Diagram

FIGURE 1. 1 OF 6 SCHMITT TRIGGERS

A

G = A

B

H = B

C

I = C

VSS

VDD

F

L = F

E

K = E

D

J = D

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1

A

2

G = A

3

B

4

H = B

5

C

6

I = C

9

D

8

J = D

11

E

10

K = E

13

F

12

L = F

1 (3, 5, 9, 11, 13)

G

*

2 (4, 6, 8, 10, 12)

BY CMOS PROTECTION

NETWORK

VDD

VSS