7-1409

CD40181BMS

TABLE A. AC TEST SETUP REFERENCE (ACTIVE LOW DATA)

TEST DELAY TIMES

AC PATHS

DC DATA INPUTS

MODE*

INPUTS

OUTPUTS

TO VSS

TO VDD

SUMIN to SUMOUT

B0

Any F

B1, B2, B3, M, Cn

All A’s

Add

SUMIN to P

A0

P

A1, A2, A3, M, Cn

All B’s

Add

SUMIN to G

B0

G

All A’s, M, Cn

B1, B2, B3

Add

SUMIN to Cn+4

B0

Cn+4

All A’s, M, Cn

B1, B2, B3

Add

Cn to SUMOUT

Cn

Any F

All A’s, M

All B’s

Add

Cn to Cn+4

Cn

Cn+4

All A’s, M

All B’s

Add

SUMIN to A = B

B0

A = B

All A’s, B1, B2, B3, M

Cn

Subtract

SUMIN to SUMOUT (Logic Mode)

All B’s

Any F

All A’s, Cn

M

Exclusive OR

* Add Mode: S0, S3 = VDD; S1, S2 = VSS.

Subtract Mode: S0, S3 = VSS; S1, S2 = VDD.

TABLE B. MAGNITUDE COMPARISON

ACTIVE HIGH DATA

ACTIVE LOW DATA

INPUT

Cn

OUTPUT

Cn+4

MAGNITUDE

INPUT

Cn

OUTPUT

Cn+4

MAGNITUDE

11

A

≤ B0

0A

≤ B

0

1

A < B

1

0

A < B

1

0

A > B

0

1

A > B

00

A

≥ B1

1A

≥ B

1 = High level

0 = Low level

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are derived from

the basic inch dimensions as indicated. Grid graduations are in mils

METALLIZATION:

Thickness: 11k

Å

PASSIVATION:

10.4kÅ - 15.6k

BOND PADS:

0.004 inches X 0.004 inches MIN

DIE THICKNESS:

0.0198 inches - 0.0218 inches