7-785

CD4027BMS

Logic Diagram

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

FUNCTION

OPEN

GROUND

VDD

9V

± -0.5V

OSCILLATOR

50kHz

25kHz

Static Burn-In 1

Note 1

1, 2, 14, 15

3 - 13

16

Static Burn-In 2

Note 1

1, 2, 14, 15

8

3 - 7, 9 - 13, 16

Dynamic Burn-

In Note 2

-

4, 7 - 9, 12

5, 6, 10, 11, 16

12, 14, 15

3, 13

Irradiation

Note 3

1, 2, 14, 15

8

3 - 7, 9 - 13, 16

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K

± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 4.75K

± 5%, VDD = 18V ± 0.5V

3. Each pin except VDD and GND will have a series resistor of 47K

± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

VDD = 10V

± 0.5V

LOGIC DIAGRAM AND TRUTH TABLE FOR CD4027BMS (ONE OF TWO IDENTICAL J-K FLIP-FLOPS)

TRUTH TABLE

PRESENT STATE

CL

*

NEXT STATE

INPUTS

OUTPUT

OUTPUTS

J

KSR

Q

Q

Q

1X0

0

0

1

0

X

000

1

1

0

0X0

0

0

0

1

X

100

1

0

1

X

X

0

0

X

No Change

X

X

10

X

X

10

X

X

01

X

X

01

X

X

11

X

X

11

Logic 1 = High Level

Logic 0 = Low Level

X = Don’t care

p

n

TG

CL

CL

p

n

TG

CL

CL

p

n

TG

CL

CL

p

n

TG

CL

CL

RESET

SET

CLOCK

CL

CL

MASTER

SLAVE

VDD

VSS

J

K

2(14)

Q

1(15)

Q

PROTECTED BY

CMOS PROTECTION

NETWORK