7-971

CD4066BMS

Schematic

FIGURE 1. SCHEMATIC DIAGRAM OF 1 OF 4 IDENTICAL SWITCHES AND ITS ASSOCIATED CONTROL CIRCUITRY

FIGURE 2. DETERMINATION OF RON AS A TEST CONDITION

FOR CONTROL INPUT HIGH VOLTAGE (VIHC)

SPECIFICATION

FIGURE 3. CHANNEL ON-STATE RESISTANCE MEASURE-

MENT CIRCUIT

FIGURE 4. CAPACITANCE TEST CIRCUIT

FIGURE 5. OFF SWITCH INPUT OR OUTPUT LEAKAGE

FIGURE 6. PROPAGATION DELAY TIME SIGNAL INPUT (VIS)

TO SIGNAL OUTPUT (VOS)

FIGURE 7. CROSSTALK CONTROL INPUT TO SIGNAL OUTPUT

IN

VSS

N

P

CONTROL

VDD

N

VC

*

P

N

VIS

OUT

VOS

SIGNAL LEVEL RANGE:

VSS

≤ VIS ≤ VDD

CONTROL

SWITCH

VSS

NORMAL OPERATION CONTROL

SWITCH ON, VC “I” = VDD

SWITCH OFF, VC “O” = VSS

NOTE:

All “P” Substrates

Connected to VDD

LINE BIASING:

ALL CONTROL INPUTS ARE

PROTECTED BY THE CMOS

PROTECTION NETWORK

*

CD4066BMS

1 OF 4 SWITCHES

IIS

VOS

VIS

|VIS - VOS|

|IIS|

RON =

TG

“ON”

VDD

VSS

10k

Ω

1k

Ω

RANGE

X-Y

PLOT TER

Y

X

H P

MOSELEY

7030A

KEITHLY 160 DIGITAL

MULTIMETER

CD4066BMS

1 OF 4 SWITCHES

VDD = +5V

VC = -5V

VSS = -5V

COS

CIS

CIOS

MEASURED ON BOONTON

CAPACITANCE BRIDGE

MODEL 75A (1MHz)

TEST FIXTURE CAPACITANCE

NULLED OUT

CD4066BMS

1 OF 4 SWITCHES

VDD

VC = VSS

VSS

ALL UNUSED TERMINALS

ARE CONNECTED TO VSS

VIS = VDD

Ι

CD4066BMS

1 OF 4 SWITCHES

VDD

VC = VDD

VSS

ALL UNUSED INPUTS

ARE CONNECTED TO VSS

ViS

50

200k

Ω

pF

VDD

tr = tf = 20ns

VOS

CD4066BMS

1 OF 4 SWITCHES

VDD

VC

VSS

ALL UNUSED TERMINALS

ARE CONNECTED TO VSS

10k

Ω

+10V

tr = tf = 20ns

VOS

1k

Ω

VIS