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CD4512BMS Datasheet(PDF) 8 Page - Intersil Corporation

Part # CD4512BMS
Description  CMOS Dual 4-Bit Latch
PDF  8 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4512BMS Datasheet(HTML) 8 Page - Intersil Corporation

  CD4512BMS Datasheet HTML 1Page - Intersil Corporation CD4512BMS Datasheet HTML 2Page - Intersil Corporation CD4512BMS Datasheet HTML 3Page - Intersil Corporation CD4512BMS Datasheet HTML 4Page - Intersil Corporation CD4512BMS Datasheet HTML 5Page - Intersil Corporation CD4512BMS Datasheet HTML 6Page - Intersil Corporation CD4512BMS Datasheet HTML 7Page - Intersil Corporation CD4512BMS Datasheet HTML 8Page - Intersil Corporation  
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7-1187
CD4512BMS
Chip Dimensions and Pad Layouts
Dimensions in parentheses are in milimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch.)
METALLIZATION:
Thickness: 11k
Å
− 14kÅ, AL.
PASSIVATION:
10.4kÅ - 15.6k
Å, Silane
BOND PADS:
0.004 inches X 0.004 inches MIN
DIE THICKNESS:
0.0198 inches - 0.0218 inches
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (“A” SELECT TO OUTPUT)
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25
oC
SUPPLY VOLTAGE (VDD) = 5V
10V
5V
LOAD CAPACITANCE (CL) (pF)
0
40
60
80
100
20
0
50
100
150
200
250
300
75
70
60
50
40
30
20
10
0
010
20
30
40
50
60
70
78
72-80
(1.829-2.032)
75-83
(1.905-2.108)
4-10
(0.102-0.254)



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