54AC00 datasheet(4/4 Pages) INTERSIL

4 / 4 page

Switching Speciﬁcations Input tr, tf = 3ns, CL = 50pF (Worst Case)

PARAMETER

SYMBOL

VCC (V)

-55oC TO 125oC

UNITS

MIN

TYP

MAX

AC TYPES

Propagation Delay, Input to Output

tPLH, tPHL

1.5

3.3 (Note 9)

3.1

10.2

5 (Note 10)

2.2

7.3 (Note 8)

Input Capacitance

Power Dissipation Capacitance

CPD (Note 11)

ACT TYPES

Propagation Delay, Input to Output

tPLH

5 (Note 10)

3.2

10.8 (Note 8)

tPHL

13.2 (Note 8)

Input Capacitance

Power Dissipation Capacitance

CPD (Note 11)

NOTES:

8. Limits tested at 100%.

9. 3.3V Min at 3.6V, Max at 3V.

10. 5V Min at 5.5V, Max at 4.5V

11. CPD is used to determine the dynamic power consumption per gate.

AC: PD = VCC

2 f

i (CPD + CL)

ACT: PD = VCC

2 f

i (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test)

DC BURN-IN I

DC BURN-IN II

OPEN

GROUND

VCC (6V)

OPEN

GROUND

VCC (6V)

CD54AC/ACT00

3, 6, 8, 11

1, 2, 4, 5, 7, 9, 10,

12, 13

3, 6, 8, 11

1, 2, 4, 5, 9, 10,

12 - 14

OPEN

GROUND

1/2 VCC (3V)

VCC (6V)

OSCILLATOR

50kHz

25kHz

CD54AC/ACT00

3, 6, 8, 11

1, 2, 4, 5, 9, 10,

12, 13

NOTE: Each pin except VCC and Gnd will have a resistor of 2kΩ-47kΩ.

DUT

OUTPUT

RL (NOTE)

OUTPUT

LOAD

500

Ω

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

FIGURE 1. PROPAGATION DELAY TIMES

CD54AC

CD54ACT

Input Level

VCC

Input Switching Voltage, VS

0.5 VCC

1.5V

Output Switching Voltage, VS

0.5 VCC

FIGURE 2. WAVEFORMS

tr = 3ns

tf = 3ns

90%

10%

GND

INPUT

tPHL

tPLH

LEVEL

CD54AC00F3A, CD54ACT00F3A

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