6-52

PARAMETER

LIMITS

UNITS

CDP1826C

(NOTE 1)

MIN

(NOTE 2)

TYP

MAX

READ - CYCLE TIMES (FIGURES 4 AND 5)

Address to TPA Setup

100

-

-

ns

Address to TPA Hold

100

-

-

ns

Access from Address Change

-

500

1000

ns

TPA Pulse Width

200

-

-

ns

Output Valid from MRD

-

500

1000

ns

Access from Chip Select

-

500

1000

ns

CEO Delay from TPA

Edge

-

150

300

ns

MRD to CEO Delay

75

-

-

ns

Output High Z from Invalid MRD

-

-

125

ns

Output High Z from Chip Deselect

-

-

225

ns

NOTES:

1. Time required by a limit device to allow tor the indicated function.

A0 - A5

LOW ORDER ADDRESS BYTE

HIGH ORDER

ADDRESS BYTE

HIGH IMPEDANCE

TPA

VALID CHIP SELECT

VALID DATA

MRD

CS1 - CS2

CEO

BUS

FIGURE 4. TIMING WAVEFORMS FOR READ CYCLE 1

CDP1826C