CDP1855CE datasheet(8/15 Pages) INTERSIL

8 / 15 page

4-54

CDP1855 Interfacing Schemes

FIGURE 3. REQUIRED CONNECTION FOR MEMORY MAPPED

ADDRESSING OF THE MDU

FIGURE 4. INTERFACING THE CDP1855 TO AN 8085 MICRO-

PROCESSOR AS AN I/O DEVICE

Programming Example for Multiplication

For a 24-bit x 24-bit multiply using the system shown in Figure 5, the following is an assembly listing of a program to multiply 201F7C16 by

723C0916:

MEMORY

LOCATION

CODE

LINE

NO.

ASSEMBLY LANGUAGE

0000

F830;

0001

LDI 030H

0002

A2;

0002

PLO R2

. . LOAD 30 INTO R2.0

0003

F800;

0003

LDI 00H

0005

B2;

0004

PHI R2

. . LOAD 00 INTO R2.1 (R2=0030)

0006

6758;

0005

OUT 7;

DC 058H

. . LOAD CONTROL REGISTERS

0008

;

0006

. . SPECIFYING THREE MDU’s

0008

;

0007

. . RESET THE Y REGISTER AND

0008

;

0008

. . SEQUENCE COUNTER

0008

6420;

0009

OUT 4;

DC 020H

. . LOAD MSB OF X REGISTER

000A

;

0010

. . WITH 20

000A

641F;

0011

OUT 4;

DC 01FH

. . LOAD NEXT MSB OF X REG

000C

;

0012

. . WITH 1F

000C

647C;

0013

OUT 4;

DC 07CH

. . LOAD LSB OF X REGISTER

000E

;

0014

. . WITH 7C

000E

6572;

0015

OUT 5;

DC 072H

. . LOAD MSB OF Z REGISTER

0010

;

0016

. . WITH 72

CLEAR

XTAL

MA0

MA1

MAX

TPA

MWR

MRD

TPB

BUS

HIGH

ADDRESS

LATCH

CDP1802

CLEAR

CLOCK

CN0

CN1

CTL

BUS

CDP1855

RA0

RA1

RE/WE

STB

RA2

+VDD

BUS 0

BUS 1

BUS 2

BUS 3

BUS 4

BUS 5

BUS 6

BUS 7

CTL

RA0

RA1

RA2

STB

RD/WE

CLK

CLEAR

CN1

CN0

VDD

VSS

IO/M

CLK (OUT)

DATA BUS

DATA

BUS

RESET OUT

1/4 CD4011

VCC

CDP1855

MDU

CDP1855, CDP1855C

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