4-89

Example 2 - Multi-PIC Application

Figure 3 shows all the connections required between CPU

and PIC’s to handle sixteen levels of interrupt control.

Register Address Assignments

The low-byte register address for any WRITE or READ

operation is the same as shown in Table 1.

The High-Byte register differs for each PIC because of the

linear addressing technique shown in the example:

The R(1) vector address is unchanged. This address will

select both PICs simultaneously (R(1). 1 = 111XXX00 =

respond when an interrupt request is serviced.

Additional PIC Application Comments

The interval select options provide significant flexibility for

interrupt routine memory allocations:

• The 2-byte interval allows one to dedicate a full page to

interrupt servicing, with variable space between routines,

by specifying indirect vectoring with 2-byte short branch

instructions on the current page.

• The 4-byte interval allows for a 3-byte long branch to any

location in memory where the interrupt service routine is

located. The branch can be preceded by a Save

Instruction to save previous contents of X and P on the

stack.

• The 8-byte and 16-byte intervals allow enough space to

perform a service routine without indirect vectoring. The

amount of interval memory can be increased even further

if all 8 INTERRUPTS are not required. Thus a 4-level inter-

rupt system could use alternate IR Inputs, and expand the

interval to 16 and 32 bytes, respectively.

• The 4 Chip Selects allow one to conserve total allotted

memory space to the PIC. For one chip, a total of 4

address lines could be used to select the device, mapping

it into as little as 4-K of memory space. Note that this

selection technique is the only one that allows the PIC to

work properly in the system: I/O mapping cannot be used

because the PIC must work within the CDP1800 interrupt

structure to define the vector address. Decoded signals

also will not work because the chip selects must be valid

on the trailing edge of TPA.

FIGURE 3. PICs AND CPU CONNECTION DIAGRAM

MA7

MA6

MA5

MA1

MWR

MRD

TPA

TPB

INT

BUS

CS

CS

MWR

MRD

TPA

TPB

INT

BUS

CDP1877

CDP1802

CPU

PIC 1

CASC

+V

IR7

IR6

IR5

IR4

IR3

IR2

IR1

IR0

MA0

CS

CS

MWR

MRD

TPA

TPB

INT

BUS

CDP1877

PIC 2

CASC

IR7

IR6

IR5

IR4

IR3

IR2

IR1

IR0

HIGHEST

PRIORITY

INTERRUPT

LOWEST

PRIORITY

INTERRUPT

CDP1877, CDP1877C