5-50

in each bit time. The parity bit (if programmed) is checked

and receipt of a valid stop bit is verified. On count 7-1/2 of

the first stop bit, the received data is loaded into the

Receiver Holding Register. If the word length is less than 8

bits, zeros (low output level) are loaded into the unused most

significant bits. If DATA AVAILABLE (DA) has not been reset

by the time the Receiver Holding Register is loaded, the

OVERRUN ERROR (OE) status bit is set. One half clock

period later, the PARITY ERROR (PE) and FRAMlNG

ERROR (FE) status bits become valid for the character in

the Receiver Holding Register. At this time, the Data

Available status bit is also set and the DATA AVAILABLE

(DA) and INTERRUPT (INT) outputs go low, signalling the

microprocessor that a received character is ready. The

microprocessor responds by executing an input instruction.

The UART’s three-state bus drivers are enabled when the

UART is selected (CS1

• CS2 • CS3 = 1) and RD/WR =

high. Status can be read when RSEL = high. Data is read

when RSEL = Iow. When reading data, TPB latches data in

the microprocessor and resets DATA AVAILABLE (DA) in the

UART. The preceding sequence is repeated for each serial

character which is received from the peripheral.

Peripheral Interface

In addition to serial data in and out, four signals are provided

for communication with a peripheral. The REQUEST TO

SEND (RTS) output signal alerts the peripheral to get ready

to receive data. The CLEAR TO SEND (CTS) input signal is

the response, signalling that the peripheral is ready. The

EXTERNAL STATUS (ES) input latches a peripheral status

level, and the PERIPHERAL STATUS INTERRUPT (PSI)

input senses a status edge (high-to-low) and also generates

an interrupt. For example, the modem DATA CARRIER

DETECT line could be connected to the PSI input on the

UART

in

order

to

signal

the

microprocessor

that

transmission failed because of loss of the carrier on the

communications line. The PSI and ES bits are stored in the

Status Register (see Table 2).

TABLE 4. CONTROL REGISTER BIT ASSIGNMENT

BIT

76543210

SIGNAL

TR

BREAK

IE

WLS2

WLS1

SBS

EPE

PI

BIT SIGNAL: FUNCTION

0

PARITY INHIBIT (PI): When set high parity generation and verification are inhibited and the PE Status bit is held low. If parity is

inhibited the stop bit(s) will immediately follow the last data bit on transmission, and EPE is ignored.

1

EVEN PARITY ENABLE (EPE): When set high, even parity is generated by the transmitter and checked by the receiver. When low,

odd parity is selected.

2

STOP BIT SELECT (SBS): See table below.

3

WORD LENGTH SELECT 1 (WLS1): See table below.

4

WORD LENGTH SELECT 2 (WLS2): See table below.

5

INTERRUPT ENABLE (lE): When set high THRE, DA, THRE

Table 1).

6

TRANSMlT BREAK (BREAK): Holds SDO low when set. Once the break bit in the control register has been set high, SDO will stay

low until the break bit is reset low and one of the following occurs: CLEAR goes low; CTS goes high; or a word is transmitted. (The

transmitted word will not be valid since there can be no start bit if SDO is already low. SDO can be set high without intermediate

transitions by transmitting a word consisting of all zeros).

7

TRANSMlT REQUEST (TR): When set high, RTS is set low and data transfer through the transmitter is initiated by the initial THRE

interrupt. (When loading the Control Register from the bus, this (TR) bit inhibits changing of other control flip-flops).

BIT 4

WLS2

BIT 3

WLS1

BIT 2

SBS

FUNCTION

0

0

0

5 data bits, 1 stop bit

0

0

1

5 data bits, 1.5 stop bits

0

1

0

6 data bits, 1 stop bit

0

1

1

6 data bits, 2 stop bits

1

0

0

7 data bits, 1 stop bit

1

0

1

7 data bits, 2 stop bits

1

1

0

8 data bits, 1 stop bit

1

1

1

8 data bits, 2 stop bits

CDP1854A, CDP1854AC