6

DG181 Series

DUAL SPST - DG181/182

TEST CONDITIONS

All Channels

All Channels

NOTE:

1. Switch states are for logic “1” input = 2.0V.

SPDT - DG187/188

TEST CONDITIONS

Channel 1

Channel 2

Channel 2

Channel 1

NOTE:

1. Switch states are for logic “1” input = 2.0V.

DUAL DPST - DG184/185

TEST CONDITIONS

All Channels

All Channels

NOTE:

1. Switch states are for logic “1” input = 2.0V.

SPDT - DG190/191

TEST CONDITIONS

Channel 1 and 2

Channel 3 and 4

Channel 3 and 4

Channel 1 and 2

NOTE:

1. Switch states are for logic “1” input = 2.0V.

NOTES:

result in spikes at leading and trailing edge of output waveform.

Switching Time Test Circuits

FIGURE 1. SWITCHING TIME TEST WAVEFORMS (Note 1)

FIGURE 2. SWITCHING TIME TEST CIRCUIT (Note 2)

50%

90%

0V

LOGIC

INPUT

SWITCH

OUTPUT

90%

SWITCH

INPUT

3V

50%

0V

LOGIC

INPUT

GND

1

k

Ω

30

SWITCH

OUTPUT

+15V

-15V

V-

SWITCH

INPUT

0V

(REPEAT TEST FOR

ALL CHANNELS)

+5V