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AD8104 Datasheet(PDF) 13 Page - Analog Devices |
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AD8104 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 36 page  AD8104/AD8105 Rev. 0 | Page 13 of 36 TRUTH TABLE AND LOGIC DIAGRAM Table 9. Operation Truth Table WE UPDATE CLK DATA INPUT DATA OUTPUT RESET SER/PAR Operation/Comment X X X X X 0 X Asynchronous reset. All outputs are disabled. Remainder of logic in 192-bit shift register is unchanged. 1 X Datai1 Datai-192 1 0 Serial mode. The data on the serial DATA IN line is loaded into the serial register. The first bit clocked into the serial register appears at DATA OUT 192 clock cycles later. 0 X X D0…D52 A0…A33 N/A in parallel mode 1 1 Parallel mode. The data on parallel lines D0 to D5 are loaded into the shift register location addressed by A0 to A3. 1 0 X X N/A in parallel mode 1 X Switch matrix update. Data in the 192-bit shift register transfers into the parallel latches that control the switch array. 1 X X X X 1 1 No change in logic. 1 Datai: serial data. 2 D0…D5: data bits. 3 A0…A3: address bits. |
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