2

HC-55564

Absolute Maximum Ratings

Thermal Information

Operating Conditions

Temperature Range

Thermal Resistance (Typical, Note 1)

θ

CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .

70

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

85

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

98

Die Characteristics

Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897

Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 x 82

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BiMOSE

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1.

θ

Electrical Specifications

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Sampling Rate

CLK

Note 2

9

16

64

kbps

Supply Current

-

0.3

1.5

mA

Logic ‘1’ Input

Note 3

3.5

-

-

V

Logic ‘0’ Input

Note 3

-

-

1.5

V

Logic ‘1’ Output

Note 4

4.0

-

-

V

Logic ‘0’ Output

Note 4

-

-

0.4

V

Clock Duty Cycle

30

-

70

%

Audio Input Voltage

AC Coupled (Note 5)

-

0.5

1.2

Audio Output Voltage

AC Coupled (Note 6)

-

0.5

1.2

Audio Input Impedance

Note 7

-

280

-

k

Ω

Audio Output Impedance

Note 7

-

150

-

k

Ω

Transfer Gain

No Load, Audio In to Audio Out.

-2.0

-

+2.0

dB

Syllabic Filter Time Constant

Note 8

-

4.0

-

ms

Signal Estimate Filter Time

Constant

Note 8

1.0

-

-

ms

Enc Threshold

-6-

Minimum Step Size

MSS

Note 10

-

0.1

-

Quieting Pattern Amplitude

FZ = 0V or APT = 0V (Note 11)

-

10

-

AGC Threshold

Note 12

-

0.1

-

F.S.

Clamping Threshold

Note 13

-

0.75

-

F.S.

NOTES:

2. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the

CVSD on the positive going edge (see Figure 2). Clock may be run at less than 9kbps and greater than 64kbps.

3. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.

changes with negative clock transitions. Each output will drive one LS TTL load.

5. Recommended voice input range for best voice performance. Should be externally AC coupled.

6. May be used for side-tone in encode mode. Should be externally AC coupled. Varies with audio input level by

±2dB.

8. Note that filter time constants are inversely proportional to clock rate. Both filters approximate single pole responses.

9. The minimum audio input voltage above which encoding takes place.

10. The minimum audio output voltage change that can be produced by the internal DAC.

11. Settled value, the “quieting” pattern or idle-channel audio output steps at one-half the bit rate, changing state on negative clock transitions.

12. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e., at

13. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of full-

scale value, and will unclamp when it falls below this value (positive or negative).