HC55182 datasheet(13/19 Pages) INTERSIL

13 / 19 page

Logic Control

Ringing patterns consist of silent intervals. The ringing to

silent pattern is called the ringing cadence. During the silent

portion of ringing, the device can be programmed to any

other operating mode. The most likely candidates are low

power standby or forward active. Depending on system

requirements, the low or high battery may be selected.

Loop supervision is provided with the ring trip detector. The ring

trip detector senses the change in loop current when the phone

is taken off hook. The loop detector full wave rectifies the

ringing current, which is then filtered with external components

RRT and CRT. The resistor RRT sets the trip threshold and the

capacitor CRT sets the trip response time. Most applications will

require a trip response time less than 150ms.

Three very distinct actions occur when the devices detects a

ring trip. First, the DET output is latched low. The latching

mechanism eliminates the need for software ﬁltering of the

detector output. The latch is cleared when the operating

mode is changed externally. Second, the VRS input is

disabled, removing the ring signal from the line. Third, the

device is internally forced to the forward active mode.

Power Dissipation

The power dissipation during ringing is dictated by the load

driving requirements and the ringing waveform. The key to valid

power calculations is the correct definition of average and RMS

currents. The average current defines the high battery supply

current. The RMS current defines the load current.

The cadence provides a time averaging reduction in the

peak power. The total power dissipation consists of ringing

power, Pr, and the silent interval power, Ps.

The terms tR and tS represent the cadence. The ringing

interval is tR and the silent interval is tS . The typical cadence

ratio tR:tS is 1:2.

The quiescent power of the device in the ringing mode is

deﬁned in Equation 34.

The total power during the ringing interval is the sum of the

quiescent power and loading power:

For sinusoidal waveforms, the average current, IAVG, is

deﬁned in Equation 36.

The silent interval power dissipation will be determined by

the quiescent power of the selected operating mode.

Forward Loop Back

Overview

The forward loop back mode (FLB, 101) provides test

capability for the device. An internal signal path is enabled

allowing for both DC and AC veriﬁcation. The internal 600

Ω

terminating resistor has a tolerance of

±20%. The device is

intended to operate from only the low battery during this

mode.

Architecture

When the forward loop back mode is initiated internal

switches connect a 600

Ω load across the outputs of the Tip

and Ring ampliﬁers.

DC Veriﬁcation

When the internal signal path is provided, DC current will

ﬂow from Tip to Ring. The DC current will force DET low,

indicating the presence of loop current. In addition, the ALM

output will also go low. This does not indicate a thermal

alarm condition. Rather, proper logic operation is veriﬁed in

the event of a thermal shutdown. In addition to verifying

device functionality, toggling the logic outputs veriﬁes the

interface to the system controller.

AC Veriﬁcation

The entire AC loop of the device is active during the forward

loop back mode. Therefore a 4-wire to 4-wire level test

capability is provided. Depending on the transhybrid balance

implementation, test coverage is provided by a one or two

step process.

System architectures which cannot disable the transhybrid

function would require a two step process. The ﬁrst step

would be to send a test tone to the device while on hook and

not in forward loop back mode. The return signal would be

the test level times the gain RF/RA of the transhybrid

ampliﬁer. Since the device would not be terminated,

cancellation would not occur. The second step would be to

program the device to FLB and resend the test tone. The

return signal would be much lower in amplitude than the ﬁrst

step, indicating the device was active and the internal

termination attenuated the return signal.

System architectures which disable the transhybrid function

would achieve test coverage with a signal step. Once the

transhybrid function is disable, program the device for FLB

and send the test tone. The return signal level is determined

by the 4-wire to 4-wire gain of the device.

RNG

--------------

(EQ. 33)

()

BHQ

BLQ

CCQ

(EQ. 34)

() VBH IAVG

RMS

REN

LOOP

------------------------------------------

–

(EQ. 35)

AVG

---





RMS

REN

LOOP

------------------------------------------

(EQ. 36)

FIGURE 10. FORWARD LOOP BACK INTERNAL TERMINATION

RING AMP

TIP AMP

RING

TIP

600

Ω

HC55180, HC55181, HC55182, HC55183, HC55184

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