183

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Ordering Information

PART NUMBER

TEMPERATURE RANGE

SCREENING LEVEL

PACKAGE

HCS160DMSR

Intersil Class S Equivalent

16 Lead SBDIP

HCS160KMSR

Intersil Class S Equivalent

16 Lead Ceramic Flatpack

HCS160D/Sample

Sample

16 Lead SBDIP

HCS160K/Sample

Sample

16 Lead Ceramic Flatpack

HCS160HMSR

Die

Die

HCS160MS

Radiation Hardened

BCD Decade Synchronous Counter

Pinouts

16 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T16, LEAD FINISH C

TOP VIEW

16 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835 CDFP4-F16, LEAD FINISH C

TOP VIEW

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

MR

CP

P0

P1

P2

P3

GND

PE

VCC

Q0

Q1

Q2

Q3

TE

SPE

TC

MR

CP

P0

P1

P2

P3

PE

GND

2

3

4

5

6

7

8

116

15

14

13

12

11

10

9

VCC

TC

Q0

Q1

Q2

Q3

TE

SPE

Features

• 3 Micron Radiation Hardened SOS CMOS

• Total Dose 200K RAD (Si)

(Typ)

• Latch-Up Free Under Any Conditions

• Fanout (Over Temperature Range)

-Standard Outputs: 10 LSTTL Loads

-Bus Driver Outputs: 15 LSTTL Loads

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

-VIL = 30% of VCC Max

-VIH = 70% of VCC Min

• Input Current Levels Ii

≤ 5µA @ VOL, VOH

Description

The Intersil HCS160MS is a Radiation Hardened high speed

presettable BCD decade synchronous counter that features an

asynchronous reset and look-ahead carry logic. Counting and

parallel presetting are accomplished synchronously with the low-

to-high transition of the clock. A low level on the synchronous

parallel enable input, SPE, disables counting and allows data at

the preset inputs, P0 - P3, to be loaded into the counter. The

counter is reset by a low on the master reset input, MR. Two count

enables, PE and TE are provided for n-bit cascading. TE also

controls the terminal count output, TC. The terminal count output

indicates a maximum count for one clock pulse and is used to

enable the next cascaded stage to count.

The HCS160MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of

radiation hardened, high-speed, CMOS/SOS Logic Family.

The HCS160MS is supplied in a 16 lead Ceramic flatpack (K suffix)

or a SBDIP Package (D suffix.)

September 1995

Spec Number

518834

File Number

2296.2