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HFA3860 Datasheet(PDF) 13 Page - Intersil Corporation

Part # HFA3860
Description  11 Mbps Direct Sequence Spread Spectrum Baseband Processor
PDF  40 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HFA3860 Datasheet(HTML) 13 Page - Intersil Corporation

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Table 7 shows examples of the bit rates and the symbol
rates and Figure 8 shows the modulation schemes.
The modulator is completely independent from the
demodulator, allowing the PRISM baseband processor to be
used in full duplex operation.
Header/Packet Description
The HFA3860 is designed to handle continuous or
packetized Direct Sequence Spread Spectrum (DSSS) data
transmissions. The HFA3860 generates its own preamble
and header information.
The device uses a synchronization preamble of up to 256
symbols, and a header that includes five fields. The
preamble is all 1's (before entering the scrambler). The
actual transmitted pattern of the preamble will be
randomized by the scrambler. The preamble is always
transmitted as a DBPSK waveform.
The five fields for the header shown in Figure 9 are:
Start Frame Delimiter (SFD) Field (16 Bits) - This
field
carries the synchronization to establish the link frame timing.
The HFA3860 will not declare a valid data packet, even if it
PN acquires, unless it detects the SFD. The HFA3860
receiver is programmed to time out searching for the SFD via
CR15. The timer starts counting the moment that initial PN
synchronization has been established from the preamble.
Signal Field (8 Bits) - This field indicates what data rate the
data packet that follows the header will be. The HFA3860
receiver looks at the signal field to determine whether it
needs to switch from DBPSK demodulation into DQPSK or
B/QMBOK demodulation at the end of the always DBPSK
preamble and header fields.
Service Field (8 Bits) - This field is currently unassigned
and can be utilized as required by the user. Set to 00h for
TABLE 7. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
DATA
MODULATION
A/D SAMPLE CLOCK
(MHZ)
TX SETUP CR 20
BITS 1, 0
RX STATUS CR 24
BITS 7, 6
DATA RATE (Mbps)
SYMBOL RATE
(MSPS)
DBPSK
44
00
00
1
1
DQPSK
44
01
01
2
1
BMBOK
44
10
10
5.5
1.375
QMBOK
44
11
11
11
1.375
802.11 DSSS BPSK
802.11 DSSS QPSK
5.5 MB/S BMBOK
11 MB/S QMBOK
1 MB/S
BARKER
2 MB/S
BARKER
DATA
IOUT
QOUT
CHIP
RATE
1 BIT ENCODED TO ONE OF
2 CODE WORDS
2 BITS ENCODED
4 CODE WORDS
4 BITS ENCODED TO ONE OF
16 MODIFIED WALSH
CODE WORDS
8 BITS ENCODED TO
256 MODIFIED WALSH
CODE WORDS
SYMBOL
RATE
I vs Q
11 MC/S
11 MC/S
11 MC/S
11 MC/S
1 MS/S
1 MS/S
1.375 MS/S
1.375 MS/S
11 CHIPS
11 CHIPS
8 CHIPS
8 CHIPS
MODIFIED
MODIFIED
(TRUE/INVERSE)
TO ONE OF
FIGURE 8. MODULATION MODES
WALSH FUNCTIONS
WALSH FUNCTIONS
ONE OF
HFA3860



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