ADE7569_15 datasheet(82/152 Pages) AD

82 / 152 page

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 82 of

152

8052 MCU CORE ARCHITECTURE

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569 have an 8052 MCU core and use the 8052 instruction

set. Some of the standard 8052 peripherals, such as the UART,

have been enhanced. This section describes the standard 8052

core and enhancements that have been made to it in the

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569.

The special function register (SFR) space is mapped into the upper

128 bytes of internal data memory space and is accessed by direct

addressing only. It provides an interface between the CPU and

all on-chip peripherals. See Figure 81 for a block diagram of the

programming model for the ADE7116/ADE7156/ADE7166/

ADE7169/ADE7566/ADE7569 via the SFR area.

All registers except the program counter (PC), instruction

reside in the SFR area. The SFR registers include control,

configuration, and data registers that provide an interface

between the CPU and all on-chip peripherals.

ENERGY

MEASUREMENT

16kB ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE

PROGRAM/DATA

MEMORY

8052

COMPATIBLE

CORE

256 BYTES XRAM

OTHER ON-CHIP

PERIPHERALS:

• SERIAL I/O

• WDT

• TIMERS

BATTERY

ADC

LCD DRIVER

TEMPERATURE

ADC

RTC

POWER

MANAGEMENT

128-BYTE

SPECIAL

FUNCTION

AREA

STACK

256 BYTES

GENERAL-

PURPOSE

RAM

BANKS

Figure 81. Block Diagram Showing Programming Model via the SFRs

MCU REGISTERS

The registers used by the MCU are summarized in this section.

Table 56. 8052 SFRs

SFR

Address

Bit Addressable

Description

ACC

0xE0

Yes

Accumulator.

0xF0

Yes

Auxiliary math.

PSW

0xD0

Yes

Program status word (see Table 57).

PCON

0x87

Program control (see Table 58).

DPL

0x82

Data pointer low (see Table 59).

DPH

0x83

Data pointer high (see Table 60).

DPTR

0x82 and 0x83

Data pointer (see Table 61).

0x81

Stack pointer (see Table 62).

CFG

0xAF

Configuration (see Table 63).

Table 57. Program Status Word SFR (PSW, Address 0xD0)

Bit

Bit Address

Mnemonic

Description

0xD7

Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD6

Auxiliary carry flag. Modified by ADD and ADDC instructions.

0xD5

General-purpose flag available to the user.

[4:3]

0xD4, 0xD3

RS1, RS0

RS1

RS0

Selected Bank

0xD2

Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD1

General-purpose flag available to the user.

0xD0

Parity bit. The number of bits set in the accumulator added to the value of the parity bit is

always an even number.

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