REV.

ADF4001

–13–

INITIALIZATION LATCH

When C2, C1 = 1, 1, the initialization latch is programmed.

This is essentially the same as the function latch (programmed

when C2, C1 = 1, 0).

However, when the initialization latch is programmed, there is

an additional internal reset pulse applied to the R and N counters.

This pulse ensures that the N counter is at a load point when

the N counter data is latched, and the device will begin counting

in close phase alignment.

If the latch is programmed for synchronous power-down (the CE

pin is high; PD1 bit is high; and PD2 bit is low), the internal

pulse also triggers this power-down. The oscillator input

buffer is unaffected by the internal reset pulse, so close phase

alignment is maintained when counting resumes.

When the first N counter data is latched after initialization, the

internal reset pulse is again activated. However, successive N

counter loads will not trigger the internal reset pulse.

DEVICE PROGRAMMING AFTER INITIAL POWER-UP

After initially powering up the device, there are three ways to

program the device.

Initialization Latch Method

Program the initialization latch (11 in 2 LSB of input word). Make

sure that F1 bit is programmed to 0.

Do an R load (00 in 2 LSBs).

Do an N load (01 in 2 LSBs).

When the initialization latch is loaded, the following occurs:

1. The function latch contents are loaded.

2. An internal pulse resets the R, N, and timeout counters to

load state conditions and also three-states the charge pump.

Note that the prescaler band gap reference and the oscillator

input buffer are unaffected by the internal reset pulse, allow-

ing close phase alignment when counting resumes.

3. Latching the first N counter data after the initialization word

will activate the same internal reset pulse. Successive N loads

will not trigger the internal reset pulse unless there is another

initialization.

CE Pin Method

Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

Program the function latch (10).

Program the R counter latch (00).

Program the N counter latch (01).

Bring CE high to take the device out of power-down. The R and

AB counters will now resume counting in close alignment.

Note that after CE goes high, a duration of 1

µs may be required

for the prescaler band gap voltage and oscillator input buffer

bias to reach steady state.

CE can be used to power the device up and down to check

for channel activity. The input register does not need to be

reprogrammed each time the device is disabled and enabled as

initially applied.

Counter Reset Method

Do a function latch load (10 in 2 LSBs). As part of this, load 1

to the F1 bit. This enables the counter reset.

Do an R counter load (00 in 2 LSBs).

Do an N counter load (01 in 2 LSBs).

Do a function latch load (10 in 2 LSBs). As part of this, load 0

to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the initial-

ization method. It offers direct control over the internal reset.

Note that counter reset holds the counters at load point and

three-states the charge pump but does not trigger synchronous

power-down. The counter reset method requires an extra func-

tion latch load compared to the initialization latch method.

APPLICATION

Extremely Stable, Low Jitter Reference Clock for GSM Base

Station Transmitter

Figure 7 shows the ADF4001 being used with a VCXO to pro-

duce an extremely stable, low jitter reference clock for a GSM

base station local oscillator (LO).

R DIVIDER

PFD

CHARGE

PUMP

N DIVIDER

1

1

LOOP

FILTER

CP

VCXO

13MHz

SYSTEM

CLOCK

ADF4110

ADF4111

ADF4112

ADF4113

LOOP

FILTER

VCO

ADF4001

13MHz

Figure 7. Low Jitter, Stable Clock Source for GSM Base

Station Local Oscillator Circuit

Typical GSM systems would have a very stable OCXO as the

clock source for the entire base station. However, distribution of

this signal around the base station makes it susceptible to

noise and spurious pickup. It is also open to pulling from the

various loads it may need to drive.

The charge pump output of the ADF4001 (Pin 2 of the TSSOP)

drives the loop filter and the 13 MHz VCXO. The VCXO output

is fed back to the RF input of the ADF4001 and also drives the

50

B