8

Compensation Break Frequency Equations

1. Pick Gain (R2/R1) for desired converter bandwidth

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 9 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual Modulator Gain has a high

gain peak due to the high Q factor of the output filter and is

not shown in Figure 9. Using the above guidelines should

give a Compensation Gain similar to the curve plotted. The

open loop error amplifier gain bounds the compensation gain.

the error amplifier. The Closed Loop Gain is constructed on

the log-log graph of Figure 9 by adding the Modulator Gain (in

dB) to the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the

transient and slow the current load rate seen by the bulk

capacitors. The bulk filter capacitor values are generally

determined by the ESR (effective series resistance) and

voltage rating requirements rather than actual capacitance

requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible.

Be careful not to add inductance in the circuit board wiring

that could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements. For example, Intel

recommends that the high frequency decoupling for the

Pentium Pro be composed of at least forty (40) 1

µF

ceramic capacitors in the 1206 surface-mount package.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

OSC

REFERENCE

ESR

ERROR

AMP

PWM

DRIVER

(PARASITIC)

-

DACOUT

R1

R3

R2

C3

C2

C1

COMP

FB

HIP6002

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

+

-

+

-

FIGURE 8. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

+

F

Z1

1

2

π R

• 2C1

•

----------------------------------

=

F

Z2

1

2

π

R1

R3

+

() C3

•

•

------------------------------------------------------

=

F

P1

1

2

π R2

•

C1

C2

•

C1

C2

+

----------------------





•

-------------------------------------------------------

=

F

1

2

π R3 C3

•

•

----------------------------------

100

80

60

40

20

0

-20

-40

-60

10M

1M

100K

10K

1K

100

10

OPEN LOOP

ERROR AMP GAIN

20LOG

COMPENSATION

FREQUENCY (Hz)

GAIN

20LOG

MODULATOR

GAIN

(R2/R1)

FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP

GAIN

HIP6002