HIP7010P datasheet(14/20 Pages) INTERSIL

14 / 20 page

During a HIP7010 reset caused by a POR, a Slow

Clock Detect, or a low on the RESET line, the

Clock Divider is inhibited and a ﬁxed divide-by six-

teen clock divider is activated. This is greater than

any selectable divide-by and guarantees proper

operation of the SERIAL interface for all valid oper-

ating frequencies (although the transfer rate will be

below 1MHz). The CLK divide-by remains at six-

teen and operation of the HIP7010 is suspended

until the Host performs a Status/Control Register

transfer to set the proper divide value. The State

Machine and SENDEC are held in a reset state

(passive) until the ﬁrst Status/Control Register

transfer has been completed. This ensures proper

setting of the divide selects prior to generation or

receipt of any symbols.

Once DS2-DS0 have been set following a reset,

they must not be altered. Each Status/Control Reg-

ister transfer must properly reassert the same

DS2-DS0 values to maintain proper clocking.

Selecting a DS2-DS0 combination which is too low

for the given CLK frequency can result in loss of

SERIAL communications, due to excessive clock-

ing rates. In such instances the only recovery

mechanism is to force a HIP7010 reset by pulling

the RESET input low, interrupting the CLK input, or

performing a power-on reset. A well behaved Host

will avoid changes to DS2-DS0. System fault toler-

ance can be maximized by using the lowest possible

frequency at the CLK input.

Power-down does not reset DS2-DS0, allowing

rapid “wake-up” from the Power-down state.

Symbol Encoder/Decoder (SENDEC)

Operation

The Symbol Encoder/Decoder (SENDEC) hardware inte-

grated in the HIP7010 handles generation and reception of

J1850 messages on a symbol by symbol basis. Symbols are

output from the SENDEC, as a digital signal, on the VPWOUT

pin and input, as a digital signal, on the VPWIN pin. These

two lines must be connected through a bus transceiver (such

as the Intersil J1850 Bus Transceiver HIP7020) to the single

wire J1850 bus. The transceiver is responsible for generating

and receiving waveforms consistent with the physical layer

speciﬁcations of J1850. In addition, the transceiver is respon-

sible for providing isolation from bus transients.

Every symbol sent out on the VPWOUT is, in effect, inverted

and

reﬂected back on the VPWIN pin after some ﬁnite delay

through the transceiver. In actuality, only active symbols are

guaranteed to be reﬂected unchanged. If the transmitted

symbol is passive and another node is simultaneously send-

ing an active symbol, the active symbol will dominate and

pull the bus to a high level. The SENDEC circuitry includes a

3-bit digital ﬁlter which effectively ﬁlters out noise pulses less

than 7

µs in duration.

The STATE logic transfers data bits between the SERIAL

system and the SENDEC, and handles addition of required

frame elements such as the SOF symbol and the CRC byte.

When transmitting bytes, bits are taken from the SERIAL

shift register and translated into the required symbols, bit by

bit. Timing of each symbol is calculated from the last

transition on the VPWIN line which keeps all nodes on the

J1850 bus “in synch” during arbitration periods.

Decoding of received symbols is automatically performed by

the SENDEC. The decoded symbol is translated to a 0 or 1

value and transferred by the STATE logic into the SERIAL shift

SERIAL shift register and, if transmitting, the next bit to transmit

on the J1850 bus is shifted out. Once an entire byte has been

loaded into the SERIAL shift register the STATE logic automati-

cally generates an unsolicited transfer of the byte to the Host.

Whenever the SENDEC is transmitting, it is simultaneously

monitoring the “reﬂected” symbol on the VPWIN line. At

each transition the reﬂected symbol is read and compared to

the sent one. If the reﬂected symbol doesn’t match the sym-

bol sent, a collision has occurred and the HIP7010 automati-

cally disables transmissions until the next Idle/IFR period. If

there was no collision, the HIP7010 continues transmitting

until the entire byte has been sent. Once the byte has been

sent, a full byte will also have been reﬂected and received by

the HIP7010. As discussed above, the HIP7010 initiates a

transfer of the received byte to the Host, which allows the

Host the opportunity to compare the sent and reﬂected

bytes, and to transfer the next byte of the message.

In addition to features already discussed, the SENDEC

includes, noise detection, Idle bus detection, a wake-up facil-

ity, “no echo” detection, and a high speed receive mode. Sym-

bol timing is based on the main CLK input. The programmable

prescaler, controlled by the DS0-DS2 bits in the Control Reg-

ister, allows proper SENDEC operation with a variety of CLK

input frequencies (see DS2-DS0 under Status/Control Reg-

ister for prescaler details). The high speed mode is a J1850

extension which allows production and/or maintenance equip-

ment to transmit messages at 4X the normal 10.4Kbps rate

(see 4X under Status/Control Register for prescaler details).

Software algorithms can be implemented in the Host to pro-

vide message buffering and ﬁltering and other needed fea-

TABLE 3. DS2-DS0 CLOCK DIVIDER SELECTIONS

DS2

DS1

DS0

CLK INPUT

FREQ. (MHZ)

INTERNAL

HIP7010 CLK

DIVIDE-BY

24 (Note 1)

001

20 (Note 1)

011

16 (Note 1)

101

110

111

NOTE:

1. Invalid operating frequency.

HIP7010

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