6-118

Functional Diagram

NOTES:

1. All lines positive logic-active high.

2. Three-state Buffers: A high

→ output active.

3. Data Latches: L high

→ Q = D and Q latches on falling edge of L.

4. Address Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E.

A

A

A4

A3

A2

LATCHED ADDRESS

REGISTER

GATED COLUMN

DECODER

AND DATA I / O

DQ0

DQ1

DQ2

DQ3

L

GATED

ROW

DECODER

32

5

5

A

A

32 x 32

MATRIX

8

8

8

8

G

LATCH

A

Q

D

L

A

LATCH

A

Q

D

L

A

LATCH

A

Q

D

L

A

LATCH

A

Q

D

L

A

S1

S2

W

E

A0

A1

A5

A6

A7

G

33

L

LATCHED

ADDRESS

REGISTER

HM-6561/883