ICL7109CPL datasheet(20/25 Pages) INTERSIL

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Test Circuit

Typical Applications

Direct Mode Interfacing

Figure 12 shows some of the combinations of chip enable

and byte enable control signals which may be used when

interfacing the ICL7109 to parallel data lines. The CE/LOAD

input may be tied low, allowing either byte to be controlled by

its own enable as in Figure 12A. Figure 12B shows a config-

uration where the two byte enables are connected together.

In this configuration, the CE/LOAD serves as a chip enable,

and the HBEN and LBEN may be connected to GND or

serve as a second chip enable. The 14 data outputs will all

be enabled simultaneously. Figure 12C shows the HBEN

and LBEN as flag inputs, and CE/LOAD as a master enable,

which could be the READ strobe available from most micro-

processors.

Figure 13 shows an approach to interfacing several

ICL7109s to a bus, connecting the HBEN and LBEN signals

of several converters together, and using the CE/LOAD

inputs (perhaps decode from an address) to select the

desired converter.

Some practical circuits utilizing the parallel three-state output

capabilities of the ICL7109 are shown in Figures 14 through

19. Figure 14 shows a straightforward application to the Intel

8048/80/85 microprocessors via an 8255PPI, where the

ICL7109 data outputs are active at all times. The I/O ports of

an 8155 may be used in the same way. This interface can be

used in a read-anytime mode, although a read performed

while the data latches are being updated will lead to

scrambled data. This will occur very rarely, in the proportion of

set-up skew times to conversion time. One way to overcome

this is to read the STATUS output as well, and if it is high, read

the data again after a delay of more than 1/2 converter clock

period. If STATUS is now low, the second reading is correct,

and if it is still high, the first reading is correct. Alternatively,

this timing problem is completely avoided by using a read-

after-update sequence, as shown in Figure 15. Here the high

to low transition of the STATUS output drives an interrupt to

the microprocessor causing it to access the data latches. This

application also shows the RUN/HOLD input being used to ini-

tiate conversions under software control.

A similar interface to Motorola MC6800 or Rockwell R650X

systems is shown in Figure 16. The high to low transition of

the STATUS output generates an interrupt via the Control

pin through Control Register B, allowing software-controlled

initiation of conversions in this system as well.

The three-state output capability of the ICL7109 allows direct

interfacing to most microprocessor busses. Examples of this

are shown in Figures 17 and 18. It is necessary to carefully

consider the system in this type of interface, to be sure that

requirements for setup and hold times, and minimum pulse

widths are met. Note also the drive limitations on long buses.

Generally this type of interface is only favored if the memory

peripheral address density is low so that simple address

decoding can be used. Interrupt handling can also require

many additional components, and using an interface device

will usually simplify the system in this case.

GND

STATUS

POL

B12

B11

B10

TEST

LBEN

HBEN

CE/LOAD

V+

REF IN -

REF CAP-

REF CAP+

REF IN+

IN HI

IN LO

COMMON

INT

BUF

REF OUT

V-

SEND

RUN/HOLD

BUF OSC OUT

OSC SEL

OSC OUT

OSC IN

MODE

GND

HIGH

ORDER

BYTE

OUTPUTS

LOW

ORDER

BYTE

OUTPUTS

+5V

BYTE

CONTROL

INPUTS

GND

V+

+5V

µF

0.01

µF

0.33

µF

0.15

µF

CAZ

CINT

RINT†

Ω

24k

Ω

3.5795MHz

TV CRYSTAL

†RINT = 20kΩ FOR 0.2V REF

= 200k

Ω FOR 2.0V REF

REF IN +

REF IN -

INPUT HIGH

INPUT LOW

GND

DIFFERENTIAL

REFERENCE

-5V

ICL7109

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