13

FN9005.4

June 10, 2005

Application Implementations

Multiple Sequencer Implementations

In order to control the sequencing of more than 4 voltages,

several of the ISL6123, ISL6124, ISL6125 or ISL6127

devices can be variously configured together to accomplish

this. There may be concerns of a particular implementation

that would make a particular configuration preferable over

another. The fundamental questions to answer to determine

which configuration is best suited for your applications are;

1. What level of voltage assurance is needed prior to

sequencing on and can the voltage supplies be grouped

into high and low criticality?

2. Is there a critical maximum time window all supplies must

be present at load or is there a first and a second group

preference possibly with some work done in between the

two groups of voltages being present?

Three configurations are described and illustrated here.

In applications where the integrity of critical voltages must be

assured prior to sequencing, additional monitoring of the

critical supplies is needed. If the compliance of the voltage is

critical for either under voltage and or over voltage the

ISL613X family of supervisors can be employed to provide

this additional assurance across multiple sequencers, see

document FN9115 for supervisor data sheet. Figure 17 is a

block diagram of this voltage compliant, high assurance, low

risk configuration showing the ISL613X supervisor and a mix

of FET switched outputs and logic output sequencers

(ISL6124 and ISL6125 ICs).

If the mere presence of some voltage potential is adequate

prior to sequencing on then a small number of standard logic

AND gates can be used to accomplish this. The block

diagram in Figure 18 illustrates this voltage presence

configuration.

In either case the sequencing is straight forward across

multiple sequencers as all DLY_ON capacitors will

simultaneously start charging ~10ms after the common

ENABLE input signal is delivered. This allows the choice of

capacitors to be related to each other no different than using

a single sequencer. When the common enabling signal is

deasserted these configurations will then execute the turn-

off sequence across all sequencers as programmed by the

DLY_OFF capacitor values.

In both cases with all the SYSRST# pins bussed together

once the on sequence is complete simultaneous shutdown

upon any UVLO input failure is assured as SYSRST# output

will momentarily pull low turning off all GATE and LOGIC

outputs.

There may be applications that require or allow groups of

supplies being brought up in sequence and supplies within

each group to be sequenced. Figure 19 illustrates such a

configuration that allows the first group of supplies to turn-on

before the second group starts. This arrangement does not

necessarily preclude adding the assurance of all supplies

prior to turn-on sequencing as previously shown but it will

FIGURE 17. ISL612X & ISL613X VOLTAGE COMPLIANT

SEQUENCING BLOCK DIAGRAM

ISL6125

ENABLE#

# N+1

ISL6124

ENABLE#

# N

ISL613Xs

MONITORING

ON ALL RAILS

UVLO

UVLO

VMON

PGOOD

G

A

T

E

L

POWER

SUPPLY

SYSRST#

SYSRST#

en

RESET#

RESET#

RESET#

O

G

I

C

OE

LOW = RESET

FIGURE 18. MULTIPLE ISL612X USING LOGIC GATES FOR

VOLTAGE PRESENCE DETECT

ISL6125

ENABLE#

# N+1

ISL6124

ENABLE#

# N

UVLO

UVLO

G

A

T

E

L

POWER

SUPPLY

SYSRST#

SYSRST#

en

RESET#’

RESET#

RESET#

O

G

I

C

UVLO

OE

LOW = RESET

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128