2

FN9062.2

April 13, 2004

Pinouts

ISL6504/A (WIDE BODY SOIC)

TOP VIEW

TOP VIEW

10

11

12

13

14

15

16

7

6

5

4

3

2

1

3V3DLSB

3V3DL

S3

1V2VID

3V3

1V5SB

5VSB

VID_PG

DLA

SS

FAULT

5VDL

S5

VID_CT

GND

5VDLSB

9

8

NOTE: SOIC layout should accomodate both wide and narrow footprints.

NOTE: The QFN bottom pad is electrically connected to the IC substrate, at

GND potential. It can be left unconnected, or connected to GND; do NOT

connect to another potential.

3V3DL

1V2VID

3V3

NC

S3

VID_PG

NC

5VDL

SS

5VDLSB

1

2

3

4

5

67

8

9

10

15

14

13

12

11

20

19

18

17

16

Ordering Information

PART NUMBER

TEMP.

PACKAGE

PKG.

DWG. #

ISL6504CB

0 to 70

16 Ld SOIC

M16.3

ISL6504CBZ

(Note)

0 to 70

16 Ld SOIC

(Pb-free)

M16.3

ISL6504CBN

0 to 70

16 Ld SOIC

M16.15

ISL6504CBNZ

(Note)

0 to 70

16 Ld SOIC

(Pb-free)

M16.15

ISL6504CR

0 to 70

20 Ld 6x6 QFN

L20.6x6

ISL6504CRZ

(Note)

0 to 70

20 Ld 6x6 QFN

(Pb-free)

L20.6x6

ISL6504EVAL1

Evaluation Board

ISL6504ACB

0 to 70

16 Ld SOIC

M16.3

ISL6504ACBZ

(Note)

0 to 70

16 Ld SOIC

(Pb-free)

M16.3

ISL6504ACBN

0 to 70

16 Ld SOIC

M16.15

ISL6504ACBNZ

(Note)

0 to 70

16 Ld SOIC

(Pb-free)

M16.15

ISL6504ACR

0 to 70

20 Ld 6x6 QFN

L20.6x6

ISL6504ACRZ

(Note)

0 to 70

20 Ld 6x6 QFN

(Pb-free)

L20.6x6

ISL6504AEVAL1

Evaluation Board

Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ISL6504, ISL6504A