ACE25C160G

Uniform SECTOR Dual and Quad Serial Flash

VER 1.5

29

Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described on page 40 can also be written to as volatile bits.

During power up reset, the non-volatile Status Register bits are copied to a volatile version of the

Status Register that is used during device operation. This gives more flexibility to change the system

configuration and memory protection schemes quickly without waiting for the typical non-volatile bit

write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile

version of the Status Register bits, the Write Enable for Volatile Status Register (50h) command

must be issued prior to each Write Status Registers (01h) command. Write Enable for Volatile Status

Register command (Figure 29) will not set the Write Enable Latch (WEL) bit, it is only valid for the

next following Write Status Registers command, to change the volatile Status Register bit values.

Figure28. Write Enable for Volatile Status Register

Power – On Timing

Table3. Power-Up Timing And Write Inhibit Threshold

Symbol

Parameter

Min

Max

Unit

tVSL

VCC(min) To CS# Low

10

us

tPUW

Time Delay From VCC(min) To Write Instruction

1

10

ms

VWI

Write Inhibit Voltage VCC(min)

1

2.5

V

Initial Delivery State

The device is delivered with the memory array erased: all bits are set to 1(each byte contains

FFH).The Status Register contains 00H (all Status Register bits are 0).