UPC8126K datasheet(8/20 Pages) NEC

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Preliminary Data Sheet P13488EJ1V0DS00

µµµµPC8126K

PIN EXPLANATIONS

No.

Symbol

Supply

Voltage

(V)

Voltage (V)

@3 V

Description

Equivalent Circuit

LOinb

–

2.6

Bypass of LO input for modulator.

This pin should be externally

grounded through around 33 pF

capacitor.

LOin

–

2.6

LO input for the phase shifter.

Connect around 300

Ω between pin

4 and 5 to match to 50

Ω by LC.

6VCC2

2.7 to 3.6

–

Supply voltage pin for the phase

shifter and IQ Mixer. An internal

regulator helps keep the device

stable against temperature or VCC

variation.

–––––––––––––

7VPS1

(Modulator)

VPS

–

Power save control pin for the

modulator can control On/Sleep

state with bias as follows.

VPS (V)

State

2.2 to 3.6

ON (Active Mode)

0 to 0.5

OFF (Sleep Mode)

9GND

(Modulator)

–

Ground pin for the modulator.

Connect to the ground with minimum

inductance.

Track length should be kept as short

as possible.

–––––––––––––

VCC/2

–

Input for I signal.

This input impedance is 180 k

Ω.

In case of that I/Q input signals are

single ended, amplitude of the signal

is 500 mVP-P max.

Note

VCC/2

–

Input for I signal.

This input impedance is 180 k

Ω.

In case of that I/Q input signals are

single ended, VCC/2 biased DC

signal should be input.

In case of that I/Q input signals are

differential, amplitude of the signal is

250 m VP-P max.

Note

Note Relations between amplitude and VCC/2 bias of input signal are following.

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