UPD16634A datasheet(13/20 Pages) NEC

13 / 20 page

Data Sheet S12595EJ2V0DS00

µµµµPD16634A

Electrical Characteristics (TA = –10 to +75

°C, VDD1 = 3.3 V ±±±± 0.3 V, VDD2 = 8.0 V ±±±± 0.5 V, VSS1 = VSS2 = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Input leakage current

IIL

±1.0

µA

High-level output voltage

VOH

STHR(STHL),IO=0 mA

VDD1

−0.1

Low-level output voltage

VOL

STHR(STHL),IO=0 mA

0.1

γ -corrected supply current

Iγ

−V9 = 8 V

V0,V9

0.3

0.6

Driver output current

IVOH

VX=7 V, VOUT=1 V

Note1

−0.5

IVOL

VX=1 V, VOUT=7 V

Note1

0.5

Output voltage deviation

Note2

∆VO

Input data : 00H to 3FH

±5

±20

Average output voltage variation

Note3

∆VAV

Input data : 00H to 3FH

±10

Output voltage range

Input data : 00H to 3FH

0.1

VDD2

−0.1

Logic part dynamic current

consumption

Notes4,5

IDD1

VDD1, when with no load

0.5

3.5

Driver part dynamic current

consumption

Notes4,5

IDD2

VDD2, when with no load

2.2

8.0

Notes 1. VX refers to the output voltage of analog output pins S1 to S300.

VOUT refers to the voltage applied to analog output pins S1 to S300.

2. The output voltage deviation refers to the voltage difference between adjoining output pins when the

display data is the same (within the chip).

3. The average output voltage variation refers to the average output voltage difference between chips. The

average output voltage refers to the average voltage between chips when the display data is the same.

4. The STB cycle is defined to be 20

µs at fCLK = 40 MHz. The TYP. values refer to an all black or all white

input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern.

5. Refers to the current consumption per driver when cascades are connected under the assumption of

SVGA single-sided mounting (10 units).

Switching Characteristics (TA =

−−−−10 to +75 °°°°C, VDD1 = 3.3 V ±±±± 0.3 V, VDD2 = 8.0 V ±±±± 0.5 V, VSS1 = VSS2 = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Start pulse delay time

tPLH1

CL = 25 pF

Driver output delay time

tPHL2

CL = 125 pF, RL = 4 k

ΩNote

3.7

µs

tPHL3

5.3

µs

tPLH2

3.0

µs

tPLH3

5.3

µs

Input capacitance

STHR,STHL excluded, TA = 25

°C

5.4

7.6

Note Load condition

output

RL = 1k

Ω

CL = 25pF

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